Patents by Inventor Sergey Voronin
Sergey Voronin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10115591Abstract: Methods and systems for selective silicon anti-reflective coating (SiARC) removal are described. An embodiment of a method includes providing a substrate in a process chamber, the substrate comprising: a resist layer, a SiARC layer, a pattern transfer layer, and an underlying layer. Such a method may also include performing a pattern transfer process configured to remove the resist layer and create a structure on the substrate, the structure comprising portions of the SiARC layer and the pattern transfer layer. The method may additionally include performing a modification process on the SiARC layer of the structure, the modification converting the SiARC layer into a porous SiARC layer. Further, the method may include performing a removal process of the porous SiARC layer of the structure, wherein the modification and removal processes of the SiARC layer are configured to meet target integration objectives.Type: GrantFiled: February 23, 2017Date of Patent: October 30, 2018Assignee: Tokyo Electron LimitedInventors: Shyam Sridhar, Li Wang, Andrew Nolan, Hiroto Ohtake, Sergey Voronin, Alok Ranjan
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Patent number: 10083820Abstract: Described herein is a technology related to a method for utilizing a dual-frequency surface wave plasma sources to provide stable ionizations on a plasma processing system. Particularly, the dual-frequency surface wave plasma sources may include a primary surface wave power plasma source and a secondary power plasma source, which is provided on each recess of a plurality of recesses. The secondary power plasma source, for example, may provide the stable ionization on the plasma processing system.Type: GrantFiled: November 14, 2017Date of Patent: September 25, 2018Assignee: Tokyo Electron LimitedInventors: Sergey A. Voronin, Jason Marion, Alok Ranjan
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Patent number: 10063062Abstract: Detecting presence or absence of plasma is accomplished from probe signals. In one embodiment, a low-power modulated signal is applied to an electrostatic chuck from a bias power generator. A corresponding system then monitors peak-to-peak voltage (Vpp) signal responses or radio frequency current responses. The probe signal can be generated to have insufficient power to either ignite or sustain plasma discharge (or cause component damage). Thus, low-duty and/or low current pulsing signals to be used. Presence or absence of the bulk plasma will then result in different Vpp or radio frequency current values.Type: GrantFiled: November 18, 2015Date of Patent: August 28, 2018Assignee: Tokyo Electron LimitedInventors: Sergey Voronin, Alok Ranjan
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Publication number: 20180197730Abstract: Methods and systems for selective silicon anti-reflective coating (SiARC) removal are described. An embodiment of a method includes providing a substrate in a process chamber, the substrate comprising: a resist layer, a SiARC layer, a pattern transfer layer, and an underlying layer. Such a method may also include performing a pattern transfer process configured to remove the resist layer and create a structure on the substrate, the structure comprising portions of the SiARC layer and the pattern transfer layer. The method may additionally include performing a modification process on the SiARC layer of the structure, the modification converting the SiARC layer into a porous SiARC layer. Further, the method may include performing a removal process of the porous SiARC layer of the structure, wherein the modification and removal processes of the SiARC layer are configured to meet target integration objectives.Type: ApplicationFiled: February 23, 2017Publication date: July 12, 2018Inventors: Shyam Sridhar, Li Wang, Andrew Nolan, Hiroto Ohtake, Sergey Voronin, Alok Ranjan
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Publication number: 20180144946Abstract: Systems and methods are disclosed for plasma discharge ignition to reduce surface particles and thereby decrease defects introduced during plasma processing. A microelectronic workpiece is positioned on a holder within a process chamber that includes a first radio frequency (RF) power source configured to couple RF power to a top portion of the process chamber, a second RF power source configured to couple RF power to the holder, and a direct current (DC) power supply. Initially, a process gas for plasma process is flowed into the process chamber. The process gas is ignited to form plasma by activating the second RF power source to apply RF power to the holder. Subsequently, the microelectronic workpiece is clamped to the holder by applying the positive voltage to the holder with the DC power supply, and the first RF power source is activated to maintain the plasma within the process chamber.Type: ApplicationFiled: November 20, 2017Publication date: May 24, 2018Applicant: TOKYO ELECTRON LIMITEDInventors: Sergey Voronin, Jason Marion, Yusuke Yoshida, Alok Ranjan, Takashi Enomoto, Yoshio Ishikawa
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Publication number: 20180138018Abstract: Described herein is a technology related to a method for utilizing a dual-frequency surface wave plasma sources to provide stable ionizations on a plasma processing system. Particularly, the dual-frequency surface wave plasma sources may include a primary surface wave power plasma source and a secondary power plasma source, which is provided on each recess of a plurality of recesses. The secondary power plasma source, for example, may provide the stable ionization on the plasma processing system.Type: ApplicationFiled: November 14, 2017Publication date: May 17, 2018Inventors: Sergey A. Voronin, Jason Marion, Alok Ranjan
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Patent number: 9966312Abstract: Techniques herein provide a chamber and substrate cleaning solution for etching and removing byproducts between separate etching steps. Such techniques include using a cleaning step based on fluorine chemistry, which is executed in between separate etch steps or divided etch steps. Such a technique can be executed in situ for improved efficiency. Other benefits include increasing etching depth/aspect ratios, and preventing post-etching defects including physical contact with neighboring gates, etc. Techniques herein are especially beneficial when applied to relatively small feature openings.Type: GrantFiled: August 22, 2016Date of Patent: May 8, 2018Assignee: Tokyo Electron LimitedInventors: Sergey Voronin, Alok Ranjan
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Publication number: 20180082903Abstract: Provided is a method of patterning structures on a substrate using an integration scheme in a patterning system, the method comprising: disposing a substrate in a processing chamber, the substrate having a plurality of structures and a pattern, the substrate including an underlying layer and a target layer, at least one structure intersecting with another structure, each intersection having an intersection angle and a corner, the integration scheme requiring a vertical corner profile at each intersection; alternatingly and sequentially etching and cleaning the substrate to transfer the pattern onto the target layer and to achieve a target vertical corner profile at each intersection; controlling selected two or more operating variables of the integration scheme in the alternating and sequential etching and cleaning operations in order to achieve target integration objectives.Type: ApplicationFiled: September 19, 2017Publication date: March 22, 2018Inventors: Sergey A. Voronin, Christopher Talone, Alok Ranjan
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Publication number: 20180019102Abstract: Embodiments of systems and methods for RF power distribution in a multi-zone electrode array are described. A system may include a plasma source configured to generate a plasma field. Also, the system may include an RF power source coupled to the plasma source and configured to supply RF power to the plasma source. The system may also include a source controller coupled to the RF power source and configured to control modulation of the RF power supplied to the plasma source to enhance uniformity of a plasma field generated by the plasma source.Type: ApplicationFiled: July 12, 2017Publication date: January 18, 2018Inventors: Sergey Voronin, Alok Ranjan
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Publication number: 20180005805Abstract: Provided are methods and systems for operation instability detection in a surface wave plasma source. In an embodiment a system for plasma processing may include a surface wave plasma source configured to generate a plasma field. The system may also include an optical sensor configured to generate information characteristic of optical energy collected in a region proximate to the surface wave plasma source. Additionally, the system may include a sensor logic unit configured to detect a region of instability proximate to the surface wave plasma source in response to the information generated by the optical sensor.Type: ApplicationFiled: January 26, 2017Publication date: January 4, 2018Inventors: Sergey Voronin, Jason Marion, Alok Ranjan
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Patent number: 9779952Abstract: Techniques herein include methods for controllable lateral etching of dielectrics in polymerizing fluorocarbon plasmas. Methods can include dielectric stack etching that uses a mask trimming step as part of a silicon etching process. Using a fluorocarbon mixture for dielectric mask trimming provides several advantages, such as being straightforward to apply and providing additional flexibility to the process flow. Thus, techniques herein provide a method to correct or tune CDs on a hardmask. In general, this technique can include using a fluorine-based and a fluorocarbon-based, or fluorohydrocarbon-based, chemistry for creating a plasma, and controlling a ratio of the two chemistries. Without the hardmask trim method disclosed herein, if a hardmask CD is not on target, then a wafer is scrapped. With hard-mask trim capability in silicon etch as disclosed herein, a given CD can be re-targeted to eliminate wafer-scraps.Type: GrantFiled: August 21, 2014Date of Patent: October 3, 2017Assignee: Tokyo Electron LimitedInventors: Alok Ranjan, Sergey Voronin
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Publication number: 20170094719Abstract: This disclosure relates to a temperature control system that may be used in a plasma processing system that treats microelectronic substrates using plasma. The temperature control system may include a heating array disposed adjacent to the microelectronic substrate and that may selectively generate heat at different portions of the microelectronic substrate. The heating array may include heating modules that selectively generate heat depending upon a breakover voltage of a Silicon Diode for Alternating Current (SIDAC). The amount of heat generated heat may depend upon the resistance of the heating module and the duty cycle of the variable voltage signal.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventors: Sergey A. Voronin, Alok Ranjan
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Publication number: 20170062225Abstract: Techniques herein provide a chamber and substrate cleaning solution for etching and removing byproducts between separate etching steps. Such techniques include using a cleaning step based on fluorine chemistry, which is executed in between separate etch steps or divided etch steps. Such a technique can be executed in situ for improved efficiency. Other benefits include increasing etching depth/aspect ratios, and preventing post-etching defects including physical contact with neighboring gates, etc. Techniques herein are especially beneficial when applied to relatively small feature openings.Type: ApplicationFiled: August 22, 2016Publication date: March 2, 2017Inventors: Sergey Voronin, Alok Ranjan
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Patent number: 9530626Abstract: A plasma processing method and apparatus are provided in which current spikes associated with application of a voltage to an electrostatic chuck (ESC) are minimized or reduced when the processing plasma is present. According to an example, the voltage is applied to the ESC after the processing plasma is struck, however the voltage is ramped or increased in a step-wise manner to achieve the desired final ESC voltage. In an alternate embodiment, the ESC voltage is at least partially applied before striking of the plasma for processing the wafer. By reducing current spikes associated with application of the voltage to the ESC during the presence of the processing plasma, transfer or deposition of particles on the wafer can be reduced.Type: GrantFiled: July 23, 2015Date of Patent: December 27, 2016Assignee: TOKYO ELECTRON LIMITEDInventors: Jason Marion, Sonam Sherpa, Sergey A. Voronin, Alok Ranjan, Yoshio Ishikawa, Takashi Enomoto
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Publication number: 20160372306Abstract: Techniques herein include a method for generating uniform plasma within an inductively-coupled plasma reactor. Techniques herein include providing a termination capacitor that is dynamically adjustable to adjust a termination capacitor value to provide a uniform E-field distribution in the reactor via a time-averaged uniformity. During a given plasma processing operation, a termination capacitor can be continuously changed to create various rotational cycles so that a given substrate received uniform treatment.Type: ApplicationFiled: November 18, 2015Publication date: December 22, 2016Inventors: Sergey Voronin, Alok Ranjan
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Publication number: 20160372933Abstract: Detecting presence or absence of plasma is accomplished from probe signals. In one embodiment, a low-power modulated signal is applied to an electrostatic chuck from a bias power generator. A corresponding system then monitors peak-to-peak voltage (Vpp) signal responses or radio frequency current responses. The probe signal can be generated to have insufficient power to either ignite or sustain plasma discharge (or cause component damage). Thus, low-duty and/or low current pulsing signals to be used. Presence or absence of the bulk plasma will then result in different Vpp or radio frequency current values.Type: ApplicationFiled: November 18, 2015Publication date: December 22, 2016Inventors: Sergey Voronin, Alok Ranjan
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Publication number: 20160027620Abstract: A plasma processing method and apparatus are provided in which current spikes associated with application of a voltage to an electrostatic chuck (ESC) are minimized or reduced when the processing plasma is present. According to an example, the voltage is applied to the ESC after the processing plasma is struck, however the voltage is ramped or increased in a step-wise manner to achieve the desired final ESC voltage. In an alternate embodiment, the ESC voltage is at least partially applied before striking of the plasma for processing the wafer. By reducing current spikes associated with application of the voltage to the ESC during the presence of the processing plasma, transfer or deposition of particles on the wafer can be reduced.Type: ApplicationFiled: July 23, 2015Publication date: January 28, 2016Applicant: TOKYO ELECTRON LIMITEDInventors: Jason MARION, Sonam SHERPA, Sergey A. VORONIN, Alok RANJAN, Yoshio ISHIKAWA, Takashi ENOMOTO
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Patent number: 9155183Abstract: The present invention provides a surface wave plasma source including an electromagnetic (EM) wave launcher comprising a slot antenna having a plurality of antenna slots configured to couple the EM energy from a first region above the slot antenna to a second region below the slot antenna, and a power coupling system is coupled to the EM wave launcher. A dielectric window is positioned in the second region and has a lower surface including the plasma surface. A slotted gate plate is arranged parallel with the slot antenna and is configured to be movable relative to the slot antenna between variable opacity positions including a first opaque position to prevent the EM energy from passing through the first arrangements of antenna slots, and a first transparent position to allow a full intensity of the EM energy to pass through the first arrangement of antenna slots.Type: GrantFiled: January 25, 2013Date of Patent: October 6, 2015Assignee: Tokyo Electron LimitedInventors: Sergey A. Voronin, Alok Ranjan
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Patent number: 9101042Abstract: A surface wave plasma source (SWPS) is disclosed, having an electromagnetic (EM) wave launcher including a slot antenna configured to couple EM energy in a desired EM wave mode to a plasma by generating a surface wave on a plasma surface of the SWPS adjacent the plasma. The SWPS also includes a dielectric window positioned below the slot antenna, having a lower surface and the plasma surface. The SWPS further includes an attenuation assembly disposed between the slot antenna and the plasma surface. The attenuation assembly includes a first fluid channel substantially aligned with a first arrangement of slots in the slot antenna, and is configured to receive a first flow of a first fluid at a first fluid temperature. The SWPS finally includes a power coupling system coupled to the EM wave launcher and configured to provide EM energy to the EM wave launcher for forming the plasma.Type: GrantFiled: December 19, 2012Date of Patent: August 4, 2015Assignee: Tokyo Electron LimitedInventors: Sergey A. Voronin, Alok Ranjan
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Publication number: 20150064918Abstract: Techniques herein include methods for controllable lateral etching of dielectrics in polymerizing fluorocarbon plasmas. Methods can include dielectric stack etching that uses a mask trimming step as part of a silicon etching process. Using a fluorocarbon mixture for dielectric mask trimming provides several advantages, such as being straightforward to apply and providing additional flexibility to the process flow. Thus, techniques herein provide a method to correct or tune CDs on a hardmask. In general, this technique can include using a fluorine-based and a fluorocarbon-based, or fluorohydrocarbon-based, chemistry for creating a plasma, and controlling a ratio of the two chemistries. Without the hardmask trim method disclosed herein, if a hardmask CD is not on target, then a wafer is scrapped. With hard-mask trim capability in silicon etch as disclosed herein, a given CD can be re-targeted to eliminate wafer-scraps.Type: ApplicationFiled: August 21, 2014Publication date: March 5, 2015Inventors: Alok Ranjan, Sergey Voronin