Patents by Inventor Serguei Okhonin
Serguei Okhonin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180292517Abstract: In some embodiments, a measurement system may include a time to digital converter (TDC) configured to determine a first digitized time at which it receives a command signal and a second digitized time at which it receives an alert signal. The first digitized time and the second digitized time may be determined for N number of iterations. The command signal may be delayed by a delay time, and the delay time may be varied for each of the N number of iterations. The measurement system may include a first dynamic photodiode (DPD) configured to switch from a reverse bias mode to an active mode based on the command signal. The TDC may calculate a difference between the first digitized time and the second digitized time for each of the N number of iterations, and the difference may vary as the delay time is varied.Type: ApplicationFiled: April 7, 2017Publication date: October 11, 2018Applicant: ActLight SAInventors: Denis SALLIN, Maxim GUREEV, Alexander KVASOV, Serguei OKHONIN
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Publication number: 20180175095Abstract: According to embodiments of the present disclosure, a dynamic photodiode may include a substrate, a first doped region, a second doped region, a first resettable doped region between the first doped region and the second doped region, and a first light absorbing region between the first doped region and the second doped region. The first doped region may include a first contact that receives a first voltage. The second doped region may include a second contact that receives a second voltage. The first resettable doped region may include a first resettable contact that receives a reset voltage or is set as an open circuit. The first light absorbing region may generate first electron-hole pairs in the substrate when the first resettable contact is set as an open circuit, and the first electron-hole pairs may be removed from the substrate when the first resettable contact receives the reset voltage.Type: ApplicationFiled: March 17, 2017Publication date: June 21, 2018Applicant: ActLight SAInventors: Denis SALLIN, Maxim GUREEV, Alexander KVASOV, Serguei OKHONIN
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Patent number: 9735304Abstract: A monolithic photo detector device disposed on a bulk substrate, comprising a photo detector disposed integrated in the bulk substrate including: (1) a p-type doped impurity region extending along a first direction in the major surface of the substrate and receiving a first voltage, (2) first and second gates being spaced apart from each other and extending in the first direction over the major surface of the substrate, wherein the gates receives a second voltage, (3) an n-type doped impurity region, extending along the first direction in the major surface of the substrate and receiving a third voltage; and (4) a light absorbing region, disposed between the second doped impurity region and the first gate. The device also includes control circuitry, integrated in the substrate to generate the first, second and third voltages that control an operating state of the detector.Type: GrantFiled: March 3, 2014Date of Patent: August 15, 2017Assignee: ACTLIGHT, S.A.Inventors: Serguei Okhonin, Maxim Gureev
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Patent number: 9431566Abstract: A photo detector comprising a first doped impurity region (adapted to receive a first voltage) disposed in or on a substrate; a body region, juxtaposed the first doped impurity region; a gate (adapted to receive a second voltage) spaced from a first portion of the body region; a light absorbing region, juxtaposed a second portion of the body region, includes a material which, in response to light incident thereon, generates carrier pairs including a first and second type carriers; a contact region (adapted to receive a third voltage) juxtaposed the light absorbing region; wherein, in response to incident light, the gate attracts first type carriers of the carrier pairs to the first portion of the body region which causes second carriers from the first doped impurity region to flow to the contact region, and the contact region attracts second type carriers.Type: GrantFiled: April 17, 2015Date of Patent: August 30, 2016Assignee: ActLight S.A.Inventor: Serguei Okhonin
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Patent number: 9425190Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.Type: GrantFiled: October 1, 2014Date of Patent: August 23, 2016Assignee: MICRON TECHNOLOGY, INC.Inventors: Yogesh Luthra, Serguei Okhonin, Mikhail Nagoga
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Patent number: 9331083Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.Type: GrantFiled: August 13, 2014Date of Patent: May 3, 2016Assignee: MICRON TECHNOLOGY, INC.Inventors: Serguei Okhonin, Viktor Koldiaev, Mikhail Nagoga, Yogesh Luthra
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Patent number: 9240496Abstract: Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor device comprising a floating gate, a control gate disposed over the floating gate, a body region that is electrically floating, wherein the body region is configured so that material forming the body region is contained under at least one lateral boundary of the floating gate, and a source region and a drain region adjacent the body region.Type: GrantFiled: July 28, 2014Date of Patent: January 19, 2016Assignee: MICRON TECHNOLOGY, INC.Inventor: Serguei Okhonin
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Patent number: 9236520Abstract: Techniques for using photo detectors as tunable proximity sensors for detection of target objects and ascertaining their distance from the proximity sensors are disclosed. In one embodiment, the techniques may be realized as a proximity sensor system including a photo detector having a first doped region, a gate, a second doped region and a light absorbing region, a control circuitry for generating a plurality of control signals to be applied to the photo detector, and a signal detector to detect an output signal from the photo detector.Type: GrantFiled: July 3, 2014Date of Patent: January 12, 2016Assignee: ACTLIGHT S.A.Inventors: Serguei Okhonin, Maxim Gureev
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Publication number: 20150221806Abstract: A photo detector comprising a first doped impurity region (adapted to receive a first voltage) disposed in or on a substrate; a body region, juxtaposed the first doped impurity region; a gate (adapted to receive a second voltage) spaced from a first portion of the body region; a light absorbing region, juxtaposed a second portion of the body region, includes a material which, in response to light incident thereon, generates carrier pairs including a first and second type carriers; a contact region (adapted to receive a third voltage) juxtaposed the light absorbing region; wherein, in response to incident light, the gate attracts first type carriers of the carrier pairs to the first portion of the body region which causes second carriers from the first doped impurity region to flow to the contact region, and the contact region attracts second type carriers.Type: ApplicationFiled: April 17, 2015Publication date: August 6, 2015Inventor: Serguei OKHONIN
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Patent number: 9012960Abstract: A photo detector comprising a first doped impurity region (adapted to receive a first voltage) disposed in or on a substrate; a body region, juxtaposed the first doped impurity region; a gate (adapted to receive a second voltage) spaced from a first portion of the body region; a light absorbing region, juxtaposed a second portion of the body region, includes a material which, in response to light incident thereon, generates carrier pairs including a first and second type carriers; a contact region (adapted to receive a third voltage) juxtaposed the light absorbing region; wherein, in response to incident light, the gate attracts first type carriers of the carrier pairs to the first portion of the body region which causes second carriers from the first doped impurity region to flow to the contact region, and the contact region attracts second type carriers.Type: GrantFiled: May 28, 2012Date of Patent: April 21, 2015Assignee: Actlight, S.A.Inventor: Serguei Okhonin
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Publication number: 20150054133Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.Type: ApplicationFiled: October 1, 2014Publication date: February 26, 2015Applicant: Micron Technology, Inc.Inventors: Yogesh LUTHRA, Serguei OKHONIN, Mikhail NAGOGA
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Publication number: 20150036425Abstract: Techniques are disclosed for writing, programming, holding, maintaining, sampling, sensing, reading and/or determining a data state of a memory cell of a memory cell array, such as a memory cell array having a plurality of memory cells each comprising an electrically floating body transistor. In one aspect, the techniques are directed to controlling and/or operating a semiconductor memory cell having an electrically floating body transistor in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the techniques may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.Type: ApplicationFiled: October 20, 2014Publication date: February 5, 2015Applicant: MICRON TECHNOLOGY, INC.Inventors: Serguei OKHONIN, Mikhail NAGOGA
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Publication number: 20140349450Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.Type: ApplicationFiled: August 13, 2014Publication date: November 27, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Serguei OKHONIN, Viktor KOLDIAEV, Mikhail NAGOGA, Yogesh LUTHRA
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Patent number: 8896082Abstract: An integrated circuit-solar cell device comprising a well region of a first dopant type, a solar cell including: (i) a first region disposed in or on the well region, wherein the first region is of the first dopant type, and (ii) a second region disposed outside the well region, wherein the second region is of a second dopant type. The device further includes an integrated circuit including: (i) a first transistor of a first type disposed in or on the well region, and (ii) a second transistor of a second type disposed in or on the first major surface of the substrate and outside the well region. Power management circuitry selectively and electrically couples the solar cell to the battery when the integrated circuit is in an inactive mode.Type: GrantFiled: February 22, 2013Date of Patent: November 25, 2014Assignee: ActLight, S.A.Inventor: Serguei Okhonin
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Publication number: 20140334229Abstract: Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor device comprising a floating gate, a control gate disposed over the floating gate, a body region that is electrically floating, wherein the body region is configured so that material forming the body region is contained under at least one lateral boundary of the floating gate, and a source region and a drain region adjacent the body region.Type: ApplicationFiled: July 28, 2014Publication date: November 13, 2014Applicant: MICRON TECHNOLOGY, INC.Inventor: Serguei OKHONIN
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Patent number: 8873283Abstract: A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell.Type: GrantFiled: October 5, 2009Date of Patent: October 28, 2014Assignee: Micron Technology, Inc.Inventors: Serguei Okhonin, Mikhail Nagoga
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Publication number: 20140312206Abstract: Techniques for using photo detectors as tunable proximity sensors for detection of target objects and ascertaining their distance from the proximity sensors are disclosed. In one embodiment, the techniques may be realized as a proximity sensor system including a photo detector having a first doped region, a gate, a second doped region and a light absorbing region, a control circuitry for generating a plurality of control signals to be applied to the photo detector, and a signal detector to detect an output signal from the photo detector.Type: ApplicationFiled: July 3, 2014Publication date: October 23, 2014Inventors: Serguei OKHONIN, Maxim GUREEV
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Patent number: 8861247Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.Type: GrantFiled: August 12, 2013Date of Patent: October 14, 2014Assignee: Micron Technology, Inc.Inventors: Yogesh Luthra, Serguei Okhonin, Mikhail Nagoga
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Patent number: 8817534Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.Type: GrantFiled: May 21, 2013Date of Patent: August 26, 2014Assignee: Micron Technology, Inc.Inventors: Serguei Okhonin, Viktor I Koldiaev, Mikhail Nagoga, Yogesh Luthra
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Patent number: 8797819Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.Type: GrantFiled: May 21, 2013Date of Patent: August 5, 2014Assignee: Micron Technology, Inc.Inventors: Eric Carman, Mikhail Nagoga, Serguei Okhonin