Patents by Inventor Seshasayee Varadarajan

Seshasayee Varadarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180047645
    Abstract: Disclosed are methods of and apparatuses and systems for depositing a film in a multi-station deposition apparatus. The methods may include: (a) providing a substrate to a first station of the apparatus, (b) adjusting the temperature of the substrate to a first temperature, (c) depositing a first portion of the material on the substrate while the substrate is at the first temperature in the first station, (d) transferring the substrate to the second station, (e) adjusting the temperature of the substrate to a second temperature, and (f) depositing a second portion of the material on the substrate while the substrate is at the second temperature, such that the first portion and the second portion exhibit different values of a property of the material. The apparatuses and systems may include a multi-station deposition apparatus and a controller having control logic for performing one or more of (a)-(f).
    Type: Application
    Filed: August 9, 2016
    Publication date: February 15, 2018
    Inventors: Seshasayee Varadarajan, Aaron R. Fellis, Andrew John McKerrow, James Samuel Sims, Ramesh Chandrasekharan, Jon Henri
  • Patent number: 9824884
    Abstract: A method of depositing silicon nitride films on semiconductor substrates processed in a micro-volume of a plasma enhanced atomic layer deposition (PEALD) reaction chamber wherein a single semiconductor substrate is supported on a ceramic surface of a pedestal and process gas is introduced through gas outlets in a ceramic surface of a showerhead into a reaction zone above the semiconductor substrate, includes (a) cleaning the ceramic surfaces of the pedestal and showerhead with a fluorine plasma, (b) depositing a halide-free atomic layer deposition (ALD) oxide undercoating on the ceramic surfaces, (c) depositing a precoating of ALD silicon nitride on the halide-free ALD oxide undercoating, and (d) processing a batch of semiconductor substrates by transferring each semiconductor substrate into the reaction chamber and depositing a film of ALD silicon nitride on the semiconductor substrate supported on the ceramic surface of the pedestal.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: November 21, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: James S. Sims, Jon Henri, Ramesh Chandrasekharan, Andrew John McKerrow, Seshasayee Varadarajan, Kathryn Merced Kelchner
  • Patent number: 9624578
    Abstract: Methods for depositing film on substrates are provided. In these embodiments, the substrates are processed in batches. Due to changing conditions within a reaction chamber as additional substrates in the batch are processed, various film properties may trend over the course of a batch. The methods herein can be used to address the trending of film properties over the course of a batch. More specifically, film property trending is minimized by changing the amount of RF power used to process substrates over the course of the batch. Such methods are sometimes referred to as RF compensation methods.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: April 18, 2017
    Assignee: Lam Research Corporation
    Inventors: Jun Qian, Frank L. Pasquale, Adrien LaVoie, Chloe Baldasseroni, Hu Kang, Shankar Swaminathan, Purushottam Kumar, Paul Franzen, Trung T. Le, Tuan Nguyen, Jennifer Petraglia, David Charles Smith, Seshasayee Varadarajan
  • Publication number: 20170092856
    Abstract: Methods of depositing silicon nitride encapsulation layers by atomic layer deposition over memory devices including chalcogenide material are provided herein. Methods include using iodine-containing silicon precursors and depositing thermally using ammonia or hydrazine as a second reactant, or iodine-containing silicon precursors and depositing using a nitrogen-based or hydrogen-based plasma.
    Type: Application
    Filed: November 6, 2015
    Publication date: March 30, 2017
    Inventors: Jon Henri, Dennis M. Hausmann, Seshasayee Varadarajan, Bhadri N. Varadarajan
  • Patent number: 9601693
    Abstract: Methods of depositing silicon nitride encapsulation layers by atomic layer deposition over memory devices including chalcogenide material are provided herein. Methods include using iodine-containing silicon precursors and depositing thermally using ammonia or hydrazine as a second reactant, or iodine-containing silicon precursors and depositing using a nitrogen-based or hydrogen-based plasma.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: March 21, 2017
    Assignee: Lam Research Corporation
    Inventors: Jon Henri, Dennis M. Hausmann, Seshasayee Varadarajan, Bhadri N. Varadarajan
  • Publication number: 20160340782
    Abstract: A showerhead in a semiconductor processing apparatus can include faceplate through-holes configured to improve the flow uniformity during atomic layer deposition. The showerhead can include a faceplate having a plurality of through-holes for distributing gas onto a substrate, where the faceplate includes small diameter through-holes. For example, the diameter of each of the through-holes can be less than about 0.04 inches. In addition or in the alternative, the showerhead can include edge through-holes positioned circumferentially along a ring having a diameter greater than a diameter of the substrate being processed. The showerhead can be a low volume showerhead and can include a baffle proximate one or more gas inlets in communication with a plenum volume of the showerhead. The faceplate with small diameter through-holes and/or edge through-holes can improve overall film non-uniformity, improve azimuthal film non-uniformity at the edge of the substrate, and enable operation at higher RF powers.
    Type: Application
    Filed: September 10, 2015
    Publication date: November 24, 2016
    Inventors: Ramesh Chandrasekharan, Saangrut Sangplung, Shankar Swaminathan, Frank Pasquale, Hu Kang, Adrien LaVoie, Edward Augustyniak, Yukinori Sakiyama, Chloe Baldasseroni, Seshasayee Varadarajan, Basha Sajjad, Jennifer L. Petraglia
  • Publication number: 20160273113
    Abstract: A method for providing an electroless plating over at least one copper containing layer is provided. Surfaces of the at least one copper containing layer are sealed by selectively depositing a sealing layer of catalytically active metal on the at least one copper containing layer. The sealing layer is exposed to an electroless deposition bath that is more reactive to the catalytically active metal than to the at least one copper containing layer to provide an electroless deposition on the sealing layer.
    Type: Application
    Filed: May 26, 2016
    Publication date: September 22, 2016
    Inventors: Artur KOLICS, Praveen NALLA, Seshasayee VARADARAJAN
  • Patent number: 9353444
    Abstract: A method for providing an electroless plating over at least one copper containing layer is provided. Surfaces of the at least one copper containing layer are sealed by selectively depositing a sealing layer of catalytically active metal on the at least one copper containing layer. The sealing layer is exposed to an electroless deposition bath that is more reactive to the catalytically active metal than to the at least one copper containing layer to provide an electroless deposition on the sealing layer.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: May 31, 2016
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, Praveen Nalla, Seshasayee Varadarajan
  • Patent number: 9309604
    Abstract: An apparatus for electroplating a layer of metal onto the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer and an auxiliary cathode located between the anode and the ionically resistive ionically permeable element. The ionically resistive ionically permeable element serves to modulate ionic current at the wafer surface. The auxiliary cathode is configured to shape the current distribution from the anode. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: April 12, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Steven Mayer, Jingbin Feng, Zhian He, Jonathan Reid, Seshasayee Varadarajan
  • Publication number: 20160090650
    Abstract: The embodiments herein relate to methods, apparatus, and systems for depositing film on substrates. In these embodiments, the substrates are processed in batches. Due to changing conditions within a reaction chamber as additional substrates in the batch are processed, various film properties may trend over the course of a batch. Disclosed herein are methods and apparatus for minimizing the trending of film properties over the course of a batch. More specifically, film property trending is minimized by changing the amount of RF power used to process substrates over the course of the batch. Such methods are sometimes referred to as RF compensation methods.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Inventors: Jun Qian, Frank L. Pasquale, Adrien LaVoie, Chloe Baldasseroni, Hu Kang, Shankar Swaminathan, Purushottam Kumar, Paul Franzen, Trung T. Le, Tuan Nguyen, Jennifer Petraglia, David Charles Smith, Seshasayee Varadarajan
  • Publication number: 20160056032
    Abstract: Disclosed are methods of depositing films of material on semiconductor substrates. The methods may include flowing a film precursor into a processing chamber through a showerhead substantially maintained at a first temperature, and adsorbing the film precursor onto a substrate held on a substrate holder such that the precursor forms an adsorption-limited layer while the substrate holder is substantially maintained at a second temperature. The first temperature may be at least about 10° C. above the second temperature, or the first temperature may be at or below the second temperature. The methods may further include removing at least some unadsorbed film precursor from the volume surrounding the adsorbed film precursor, and thereafter reacting adsorbed film precursor to form a film layer. Also disclosed herein are apparatuses having a processing chamber, a substrate holder, a showerhead, and one or more controllers for operating the apparatus to employ the foregoing film deposition techniques.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 25, 2016
    Inventors: Chloe Baldasseroni, Adrien LaVoie, Hu Kang, Jun Qian, Purushottam Kumar, Andrew Duvall, Cody Barnett, Mohamed Sabri, Ramesh Chandrasekharan, Karl F. Leeser, David C. Smith, Seshasayee Varadarajan, Edmund B. Minshall
  • Publication number: 20150315720
    Abstract: An electroplating apparatus for filling recessed features on a semiconductor substrate includes a vessel configured to maintain a concentrated electroplating solution at a temperature of at least about 40° C., wherein the solution would have formed a precipitate at 20° C. This vessel is in fluidic communication with an electroplating cell configured for bringing the concentrated electrolyte in contact with the semiconductor substrate at a temperature of at least about 40° C., or the vessel is the electroplating cell. In order to prevent precipitation of metal salts from the electrolyte, the apparatus further includes a controller having program instructions for adding a diluent to the concentrated electroplating solution in the vessel to avoid precipitation of a salt from the concentrated electroplating solution in response to a signal indicating that the electrolyte is at risk of precipitation.
    Type: Application
    Filed: July 15, 2015
    Publication date: November 5, 2015
    Inventors: Steven T. Mayer, Jonathan David Reid, Seshasayee Varadarajan
  • Publication number: 20150275374
    Abstract: A method for providing an electroless plating over at least one copper containing layer is provided. Surfaces of the at least one copper containing layer are sealed by selectively depositing a sealing layer of catalytically active metal on the at least one copper containing layer. The sealing layer is exposed to an electroless deposition bath that is more reactive to the catalytically active metal than to the at least one copper containing layer to provide an electroless deposition on the sealing layer.
    Type: Application
    Filed: March 25, 2014
    Publication date: October 1, 2015
    Inventors: Artur KOLICS, Praveen NALLA, Seshasayee VARADARAJAN
  • Patent number: 9109295
    Abstract: An electroplating apparatus for filling recessed features on a semiconductor substrate includes an electrolyte concentrator configured for concentrating an electrolyte having Cu2+ ions to form a concentrated electrolyte solution that would have been supersaturated at 20° C. The electrolyte is maintained at a temperature that is higher than 20° C., such as at least at about 40° C. The apparatus further includes a concentrated electrolyte reservoir and a plating cell, where the plating cell is configured for electroplating with concentrated electrolyte at a temperature of at least about 40° C. Electroplating with electrolytes having Cu2+ concentration of at least about 60 g/L at temperatures of at least about 40° C. results in very fast copper deposition rates, and is particularly well-suited for filling large, high aspect ratio features, such as through-silicon vias.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: August 18, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Seshasayee Varadarajan, Steven T. Mayer
  • Patent number: 9045841
    Abstract: In a copper electroplating apparatus having separate anolyte and catholyte portions, the concentration of anolyte components (e.g., acid or copper salt) is controlled by providing a diluent to the recirculating anolyte. The dosing of the diluent can be controlled by the user and can follow a pre-determined schedule. For example, the schedule may specify the diluent dosing parameters, so as to prevent precipitation of copper salt in the anolyte. Thus, precipitation-induced anode passivation can be minimized.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: June 2, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Bryan Buckalew, Jonathan Reid, John Sukamto, Zhian He, Seshasayee Varadarajan, Steven T. Mayer
  • Patent number: 9029258
    Abstract: To achieve the foregoing and in accordance with the purpose of the present invention, a method for filling through silicon vias is provided. A dielectric layer is formed over the through silicon vias. A barrier layer, comprising tungsten, is deposited by CVD or ALD over the dielectric layer. The through silicon vias are filled with a conductive material.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: May 12, 2015
    Assignee: Lam Research Corporation
    Inventors: Praveen Reddy Nalla, Novy Sastrawati Tjokro, Artur Kolics, Seshasayee Varadarajan
  • Publication number: 20140217590
    Abstract: To achieve the foregoing and in accordance with the purpose of the present invention, a method for filling through silicon vias is provided. A dielectric layer is formed over the through silicon vias. A barrier layer, comprising tungsten, is deposited by CVD or ALD over the dielectric layer. The through silicon vias are filled with a conductive material.
    Type: Application
    Filed: February 5, 2013
    Publication date: August 7, 2014
    Applicant: Lam Research Corporation
    Inventors: Praveen Reddy NALLA, Novy Sastrawati TJOKRO, Artur KOLICS, Seshasayee VARADARAJAN
  • Publication number: 20130327650
    Abstract: An apparatus for electroplating a layer of metal onto the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer and an auxiliary cathode located between the anode and the ionically resistive ionically permeable element. The ionically resistive ionically permeable element serves to modulate ionic current at the wafer surface. The auxiliary cathode is configured to shape the current distribution from the anode. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 12, 2013
    Inventors: Steven Mayer, Jingbin Feng, Zhian He, Jonathan Reid, Seshasayee Varadarajan
  • Publication number: 20130237063
    Abstract: A split-pumping system and method for semiconductor fabrication process chambers is provided. The split pumping method may provide two separate exhaust paths, each configured to evacuate a different process gas. The exhaust paths may be configured to not evacuate process gases other than the process gas that the exhaust path is configured to evacuate.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 12, 2013
    Inventors: SESHASAYEE VARADARAJAN, ANTONIO XAVIER, Ramesh CHANDRASEKHARAN, DIRK RUDOLPH
  • Patent number: 8475636
    Abstract: An apparatus for electroplating a layer of metal onto the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer and an auxiliary cathode located between the anode and the ionically resistive ionically permeable element. The ionically resistive ionically permeable element serves to modulate ionic current at the wafer surface. The auxiliary cathode is configured to shape the current distribution from the anode. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: July 2, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Steven Mayer, Jingbin Feng, Zhian He, Jonathan Reid, Seshasayee Varadarajan