Abstract: A semiconductor device includes a plurality of word lines extending in a first direction; a plurality of bit lines extending in a second direction crossing the first direction; a plurality of memory cells in a plurality of areas in which the plurality of word lines and the plurality of bit lines intersect; and a semiconductor element connected to at least one of the plurality of word lines and the plurality of bit lines, the semiconductor element including a first active pattern and a second active pattern overlapping the first active pattern along a height direction perpendicular to the first and second directions.

Abstract: A vertical semiconductor switching device includes lower and upper conductive patterns, and an active pattern electrically connected between the lower conductive pattern and the upper conductive pattern. The active pattern includes a lower source/drain (S/D) region electrically coupled to the lower conductive pattern, an upper S/D region electrically coupled to the upper conductive pattern, and a channel region having first impurities of a first conductivity type therein, electrically connected to the lower source/drain region and to the upper source/drain region. The channel region includes a lower channel region, an intermediate channel region on the lower channel region, and an upper channel region on the intermediate channel region. A gate electrode is provided on a side surface of the channel region.

Abstract: A memory device includes word lines, bit lines, memory cells, and a circuit. The circuit applies a first voltage to a first bit line of a target memory cell, applies a second voltage to a first word line of the target memory cell, and performs at least one of a first operation and a second operation. The first operation includes applying an adjustment voltage to a second bit line or second word line connected to an adjacent initialized memory cell, and the second operation includes applying a third voltage of an opposite polarity to the first voltage to a third bit line of a next target memory cell that is initialized after initialization of the target memory cell and applying a fourth voltage of an opposite polarity to the second voltage to a third word line of the next target memory cell.

Abstract: A method of reading data from a self-selecting memory includes generating a read pulse that has a polarity opposite to that of a write pulse. The write pulse writes data into a target memory cell in the self-selecting memory. The read pulse is applied to the target memory cell. The read pulse has a first edge that is a starting point of the read pulse and a second edge that is an ending point of the read pulse. A slope of the second edge of the read pulse is adjusted such that an undershoot or overshoot on the second edge of the read pulse increases.

Abstract: A semiconductor memory device includes an active portion, a pad insulating layer on the active portion and including a pad through hole, a landing pad in the pad through hole and electrically connected to the active portion, and the landing pad including a protrusion protruding towards an upper portion of the pad insulating layer, a lower conductive layer on the pad insulating layer and bordering a side surface of the protrusion of the landing pad, a lower electrode on the landing pad and electrically connected to the landing pad, a ferroelectric layer on the lower conductive layer and bordering the lower electrode, an upper electrode bordering the ferroelectric layer, an electrode insulating layer on the upper electrode, a plate line on the electrode insulating layer and the upper electrode and electrically connected to the upper electrode, wherein the plate line is electrically connected to the lower conductive layer through a through via.

Abstract: According to an aspect of the disclosure, a vertical memory device may include: a substrate; a plurality of electrode structures extending in a vertical direction on the substrate; a word line cut disposed apart from the plurality of electrode structures in a horizontal direction and extending in the vertical direction; and a gate stack structure may include gate electrodes and interlayer insulating layers alternately stacked on the substrate along a sidewall of each of the plurality of electrode structures and the word line cut, wherein the gate electrodes may be electrically connected to the plurality of electrode structures. In a plan view, the word line cut may be wavy-shaped.

Abstract: A memory device including a ferroelectric cell capacitor, and an operating method thereof. For example, an operating method of a memory device, according to some embodiments, may include pre-charging a bit line to a pre-charge voltage, the bit line connected to a ferroelectric cell capacitor to be written to, writing data into the ferroelectric cell capacitor by adjusting a level of a voltage applied to a bit line and a word line corresponding to the ferroelectric cell capacitor, and deactivating the word line, wherein a voltage applied to a plate line connected to the ferroelectric cell capacitor is maintained at a ground voltage during the writing of the data into the ferroelectric cell capacitor.

Abstract: A semiconductor chip includes a logic core layer that receives input data from an external host and calculates an inference value based on the input data, a redistribution wiring layer provided on the logic core layer, wherein the redistribution wiring layer includes a plurality of redistribution wirings, which transmit the input data, and an insulating layer, which covers the plurality of redistribution wirings, and a weight storage layer provided on the redistribution wiring layer, wherein the weight storage layer includes a plurality of memory cells, each of which store weights for calculating the inference value through amorphous materials, wherein the weights are transmitted to the logic core layer through the plurality of redistribution wirings according to the input data.

Abstract: A memory device includes a first conductive line, a second conductive line, and a memory cell disposed between the first and second conductive lines. The memory cell includes a lower electrode layer, a switching pattern, and an upper electrode layer. The switching pattern includes a main region including a pair of first side walls and a pair of second walls, and a corner region at four corners of the main region. The switching pattern includes a chalcogenide layer including a Group VI chalcogen element, an element of Group IV and an element of Group V, and the concentration of the Group IV element in the corner region is greater than that of the Group IV element in the main region, or the concentration of the Group V element in the corner region is greater than that of the Group V element in the main region.

Abstract: Provided is a semiconductor memory device including: cell blocks, each including a folding structure in which electrode structures and insulating structures are alternately provided, wherein the electrode structures and the insulating structures extend in a vertical direction and are connected with each other so as to have at least two U-shaped structures forming villus shapes in a plan view, the electrode structures include a vertical electrode and a switching material layer, and the cell blocks are provided in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction; and a gate stack structure including gate electrodes and interlayer insulating layers that are alternately stacked in the vertical direction along sidewalls of the electrode structures.

Abstract: A semiconductor device includes first and second conductive lines respectively extending in first and second directions on a substrate. Cell structures are respectively between the first and second conductive lines and include first and second electrodes and a selector layer. First capping layers cover side surfaces of the first conductive lines and first side surfaces of the cell structures in the second direction. First interlayer insulating layers fill spaces between the first conductive lines and between the cell structures in the second direction and contact the first capping layers. Second capping layers cover second side surfaces of the cell structures in the first direction and side surfaces of the second conductive lines. Second interlayer insulating layers fill spaces between the cell structures and between the second conductive lines in the first direction and contact the second capping layers. The first and second interlayer insulating layers have different carbon contents.

Abstract: A semiconductor memory device is provided. The semiconductor device includes: a stacked structure with word line plates and mold insulating layers which extend in first and second horizontal directions, and are alternately stacked in a vertical direction in a cell array region and an extension region, the plurality of word line plates forming a staircase structure in the extension region; a vertical bit line extending into the stacked structure in the cell array region; a plurality of selection layers between the plurality of word line plates and the vertical bit line; and a vertical channel transistor connected to one end of the vertical bit line. A first thickness of each of the plurality of mold insulating layers is about 1.5 times to about 3 times a second thickness of each of the plurality of word line plates.

Abstract: A three-dimensional memory device includes a base dielectric layer disposed on a substrate, a stack structure that includes word lines and interlayer dielectric layers that are alternately stacked on the base dielectric layer, a bit line that penetrates the stack structure and extends in a vertical direction perpendicular to a top surface of the substrate, and buried storage patterns interposed between the bit line and the word lines and spaced apart from each other in the vertical direction. Each of the buried storage patterns has a width in a horizontal direction parallel to the top surface of the substrate. The widths of the buried storage patterns increase with increasing vertical distance from the substrate.

Abstract: A vertical channel transistor includes a substrate having a bit line thereon, and a vertical channel layer including a first metal oxide, on the bit line. A lower insertion layer is provided, which extends between the bit line and a first end of the channel layer, and includes a second metal oxide having a greater bonding energy relative to the first metal oxide. A lower source/drain region is provided, which extends between the first end of the channel layer and the lower insertion layer, and includes a first metal dopant that is a reduced form of the first metal oxide. An upper source/drain region is provided, which is electrically connected to a second end of the channel layer, and includes the first metal dopant. An insulated gate line is provided on the channel layer.

Abstract: An integrated circuit device including first and second vertical transistors, wherein the first and second vertical transistors are apart from each other in a first direction; a common plate between the first and second vertical transistors; a first capacitor structure between the first vertical transistor and the common plate including a first lower electrode extending in the first direction, a first dielectric layer on the first lower electrode, and a first upper electrode on the first dielectric layer; and a second capacitor structure between the second vertical transistor and the common plate including a second lower electrode extending in the first direction, a second dielectric layer on the second lower electrode, and a second upper electrode on the second dielectric layer, wherein the first upper electrode is on a lower surface of the common plate, and the second upper electrode is on an upper surface of the common plate.

Abstract: A three-dimensional memory device includes a base insulating layer on a substrate, a stack structure including word lines and first interlayer insulating layers which are alternately stacked on the base insulating layer, and a second interlayer insulating layer on an uppermost one of the word lines, bit lines that are in the stack structure and spaced apart from each other in a first direction parallel to a top surface of the substrate, each bit line including a first portion that protrudes from a top surface of the stack structure and a second portion that are in the stack structure, an outer electrode on the stack structure and on the first portions of the bit lines, and a dielectric layer between the outer electrode and the first portion of the bit line and surrounding a side surface of the first portion of the bit line in plan view.

Abstract: A vertical memory device includes a memory cell structure extending primarily in a vertical direction. A resistive layer is electrically connected to a first end of the memory cell structure. A selector is electrically connected to a second end of the memory cell structure and includes a variable resistive material of which an electrical resistive value is reversibly changed in response to an electrical signal. A first bit line is located apart from the memory cell structure in the vertical direction with the resistive layer disposed therebetween and is connected to the resistive layer. A second bit line is located apart from the memory cell structure in the vertical direction with the selector disposed therebetween and is connected to the selector. A plurality of word line plates are spaced apart from each other in the vertical direction and overlapping each other in the vertical direction. Each word line plate at least partially surrounds a portion of a sidewall of the memory cell structure.

Abstract: A 3D vertical memory device includes a substrate and an electrode structure extending in a vertical direction on the substrate. The electrode structure has a shape of a first cylinder and includes a first electrode and a switching material layer. A gate stack structure includes a gate electrode and an interlayer insulating layer alternately stacked on the substrate along a sidewall of the electrode structure. The gate electrode is electrically connected to the switching material layer. The electrode structure is arranged in a two-dimensional array structure on a plane perpendicular to the vertical direction, and constitutes a plurality of lines extending in a first direction. The electrode structures of two lines adjacent to each other in a second direction are arranged in a zigzag manner. A partition wall pillar having a shape of a second cylinder is arranged between the electrode structures adjacent to each other in the first direction.

Abstract: A memory device includes a first conductive line extending in a first horizontal direction, a second conductive line extending in a second horizontal direction, and a memory cell extending in a vertical direction between the first conductive line and the second conductive line. The memory cell includes a lower electrode layer, a switching pattern, and an upper electrode layer, which are sequentially stacked on the first conductive line. The switching pattern includes a chalcogenide layer including a chalcogen element of group VI of the periodic table, and an element of group IV and an element of group V of the periodic table, which are chemically bonded to the group VI chalcogen element. The switching pattern is configured to have a three-level concentration gradient of the group IV element or the group V element in the vertical direction.

Abstract: A semiconductor memory device includes a first source line extending in a first horizontal direction, a second source line extending on the first source line in the first horizontal direction, a plurality of word line plates arranged apart from each other in a vertical direction, between the first source line and the second source line, a vertical bit line configured to penetrate the plurality of word line plates and extending in the vertical direction, a selector arranged between the plurality of word line plates and the vertical bit line, a first vertical channel transistor arranged between the vertical bit line and the first source line, and a second vertical channel transistor arranged between the vertical bit line and the second source line.