Patents by Inventor Seung Beom Baek
Seung Beom Baek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10186597Abstract: A method for fabricating a semiconductor device includes: forming a semiconductor structure including a pattern; forming an epitaxial layer having a first dopant concentration in the pattern; forming in-situ an interface layer having a second dopant concentration higher than the first dopant concentration, over the epitaxial layer; forming a metal silicide layer over the interface layer; and forming a metal plug over the metal silicide layer.Type: GrantFiled: February 13, 2018Date of Patent: January 22, 2019Assignee: SK Hynix Inc.Inventors: Tae-Hang Ahn, Oh-Hyun Kim, Seung-Beom Baek
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Publication number: 20180182861Abstract: A method for fabricating a semiconductor device includes: forming a semiconductor structure including a pattern; forming an epitaxial layer having a first dopant concentration in the pattern; forming in-situ an interface layer having a second dopant concentration higher than the first dopant concentration, over the epitaxial layer; forming a metal silicide layer over the interface layer; and forming a metal plug over the metal silicide layer.Type: ApplicationFiled: February 13, 2018Publication date: June 28, 2018Inventors: Tae-Hang AHN, Oh-Hyun KIM, Seung-Beom BAEK
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Patent number: 9929249Abstract: A method for fabricating a semiconductor device includes: forming a semiconductor structure including a pattern; forming an epitaxial layer having a first dopant concentration in the pattern; forming in-situ an interface layer having a second dopant concentration higher than the first dopant concentration, over the epitaxial layer; forming a metal silicide layer over the interface layer; and forming a metal plug over the metal silicide layer.Type: GrantFiled: August 9, 2017Date of Patent: March 27, 2018Assignee: SK Hynix Inc.Inventors: Tae-Hang Ahn, Oh-Hyun Kim, Seung-Beom Baek
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Patent number: 9831344Abstract: A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.Type: GrantFiled: February 23, 2017Date of Patent: November 28, 2017Assignee: SK Hynix Inc.Inventors: Oh-Hyun Kim, Seung-Beom Baek, Tae-Hang Ahn
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Publication number: 20170186870Abstract: A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.Type: ApplicationFiled: February 23, 2017Publication date: June 29, 2017Inventors: Oh-Hyun KIM, Seung-Beom BAEK, Tae-Hang AHN
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Patent number: 9614084Abstract: A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.Type: GrantFiled: July 7, 2016Date of Patent: April 4, 2017Assignee: SK Hynix Inc.Inventors: Oh-Hyun Kim, Seung-Beom Baek, Tae-Hang Ahn
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Patent number: 9520186Abstract: A semiconductor memory may include: a first stacked structure including a first word line disposed over a substrate and extended in a first direction, a first bit line disposed over the first word line and extended in a second direction crossing the first direction, and a first variable resistance layer interposed between the first word line and the first bit line; and a second stacked structure including a second bit line disposed over the first stacked structure and extended in the second direction, a second word line disposed over the second bit line and extended in the first direction, and a second variable resistance layer interposed between the second word line and the second bit line; and a first selecting element layer interposed between the first bit line and the second bit line.Type: GrantFiled: February 7, 2014Date of Patent: December 13, 2016Assignee: SK HYNIX INC.Inventors: Hyo-June Kim, Ja-Chun Ku, Sung-Kyu Min, Seung-Beom Baek, Byung-Jick Cho, Won-Ki Ju, Hyun-Kyu Kim, Jong-Chul Lee
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Patent number: 9305775Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.Type: GrantFiled: March 25, 2015Date of Patent: April 5, 2016Assignee: SK Hynix Inc.Inventors: Young Ho Lee, Keum Bum Lee, Min Yong Lee, Hyung Suk Lee, Seung Beom Baek
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Patent number: 9159632Abstract: A method of fabricating a semiconductor apparatus includes forming an insulating layer on a semiconductor substrate, forming a source post in the insulating layer, and forming a semiconductor layer over the source post and the insulating layer.Type: GrantFiled: March 18, 2013Date of Patent: October 13, 2015Assignee: SK Hynix Inc.Inventors: Young Ho Lee, Seung Beom Baek
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Patent number: 9105840Abstract: According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern.Type: GrantFiled: March 6, 2014Date of Patent: August 11, 2015Assignee: SK HYNIX INC.Inventors: Jong-Chul Lee, Ja-Chun Ku, Sung-Kyu Min, Byung-Jick Cho, Seung-Beom Baek, Hyo-June Kim, Won-Ki Ju, Hyun-Kyu Kim
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Publication number: 20150200088Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.Type: ApplicationFiled: March 25, 2015Publication date: July 16, 2015Inventors: Young Ho LEE, Keum Bum LEE, Min Yong LEE, Hyung Suk LEE, Seung Beom BAEK
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Patent number: 9054128Abstract: A doping method that forms a doped region at a desired location of a three-dimensional (3D) conductive structure, controls the doping depth and doping dose of the doped region relatively easily, has a shallow doping depth, and prevents a floating body effect. A semiconductor device is fabricated using the same doping method. The method includes, forming a conductive structure having a sidewall, exposing a portion of the sidewall of the conductive structure, and forming a doped region in the exposed portion of the sidewall by performing a plasma doping process.Type: GrantFiled: February 20, 2014Date of Patent: June 9, 2015Assignee: SK Hynix Inc.Inventors: Jin-Ku Lee, Jae-Geun Oh, Young-Ho Lee, Mi-Ri Lee, Seung-Beom Baek
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Patent number: 9018612Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.Type: GrantFiled: December 13, 2012Date of Patent: April 28, 2015Assignee: SK Hynix Inc.Inventors: Young Ho Lee, Keum Bum Lee, Min Young Lee, Hyung Suk Lee, Seung Beom Baek
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Publication number: 20150085559Abstract: According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern.Type: ApplicationFiled: March 6, 2014Publication date: March 26, 2015Applicant: SK HYNIX INC.Inventors: Jong-Chul LEE, Ja-Chun KU, Sung-Kyu MIN, Byung-Jick CHO, Seung-Beom BAEK, Hyo-June KIM, Won-Ki JU, Hyun-Kyu KIM
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Publication number: 20150089087Abstract: A semiconductor memory may include: a first stacked structure including a first word line disposed over a substrate and extended in a first direction, a first bit line disposed over the first word line and extended in a second direction crossing the first direction, and a first variable resistance layer interposed between the first word line and the first bit line; and a second stacked structure including a second bit line disposed over the first stacked structure and extended in the second direction, a second word line disposed over the second bit line and extended in the first direction, and a second variable resistance layer interposed between the second word line and the second bit line; and a first selecting element layer interposed between the first bit line and the second bit line.Type: ApplicationFiled: February 7, 2014Publication date: March 26, 2015Applicant: SK HYNIX INC.Inventors: Hyo-June KIM, Ja-Chun KU, Sung-Kyu MIN, Seung-Beom BAEK, Byung-Jick CHO, Won-Ki JU, Hyun-Kyu KIM, Jong-Chul LEE
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Patent number: 8980683Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.Type: GrantFiled: July 3, 2014Date of Patent: March 17, 2015Assignee: SK Hynix Inc.Inventors: Min Yong Lee, Young Ho Lee, Seung Beom Baek, Jong Chul Lee
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Patent number: 8921208Abstract: A method for fabricating a semiconductor device includes forming a first insulating layer in a first area of the semiconductor substrate, lowering a height of the semiconductor substrate in a second area and a height of the first insulating layer in the first area, selectively forming a sacrificial layer in the second area using the first insulating layer as a growth prevention layer, and forming a first semiconductor layer on the semiconductor substrate including the sacrificial layer.Type: GrantFiled: January 16, 2014Date of Patent: December 30, 2014Assignee: SK Hynix Inc.Inventors: Seung Beom Baek, Bo Min Park, Young Ho Lee, Jong Chul Lee
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Patent number: 8890104Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.Type: GrantFiled: August 29, 2012Date of Patent: November 18, 2014Assignee: SK Hynix Inc.Inventors: Min Yong Lee, Young Ho Lee, Seung Beom Baek, Jong Chul Lee
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Publication number: 20140322886Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.Type: ApplicationFiled: July 3, 2014Publication date: October 30, 2014Inventors: Min Yong LEE, Young Ho LEE, Seung Beom BAEK, Jong Chul LEE
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Publication number: 20140179069Abstract: A method of fabricating a semiconductor apparatus includes forming an insulating layer on a semiconductor substrate, forming a source post in the insulating layer, and forming a semiconductor layer over the source post and the insulating layer.Type: ApplicationFiled: March 18, 2013Publication date: June 26, 2014Applicant: SK HYNIX INC.Inventors: Young Ho LEE, Seung Beom BAEK