Abstract: An online fitting method and apparatus receive, from a user, a body size of the user and a target size of clothes desired by the user for fitting, obtain barycentric coordinate information corresponding to a result of fitting the clothes of the target size to a reference avatar selected based on the body size of the user, generate a target avatar having the same mesh topology as the reference avatar and corresponding to the body size of the user, fit the clothes to the target avatar by applying the barycentric coordinate information to the target avatar, and display a result of fitting the clothes to the target avatar.

Abstract: An LCD device and a method of driving the same are provided. The LCD device includes a panel, one or more gate driver IC, a timing controller, and a source driver IC. The gate driver IC sequentially drives a plurality of gate lines formed in the panel. The timing controller controls the gate driver IC. The source driver IC simultaneously transfers image data from a first latch to a second latch according to a latch signal, converts the image data transferred from the second latch into data voltages, and outputs the data voltages to the panel at a falling time of a source output enable signal.

Abstract: Disclosed is a display device. The display device includes a plurality of MCC packages each including one source driver IC and one gate driver IC disposed on a film, a panel including a plurality of data lines connected to the source driver IC, a plurality of gate connection lines that are connected to the gate driver IC and disposed in parallel to the data lines, a plurality of gate lines that are disposed vertically to the gate connection lines and the data lines and connected to the gate connection lines, and a plurality of dummy lines disposed in parallel to the gate connection lines and between the data lines, and a timing controller configured to transfer image data and a plurality of control signals to at least one or more of the MCC packages.

Abstract: An image display device and a method of driving the same, which reduce the number of transmission/reception lines of image data using a multi-drop intra-panel interface as well as to improve the bandwidth use efficiency. The image display device includes: an image display panel configured to display an image by including a plurality of pixel regions; a plurality of first gate integrated circuits (ICs) located at a first side of the image display panel so as to drive gate lines of the liquid crystal panel; a plurality of data integrated circuits (ICs) configured to drive data lines of the image display panel; and a timing controller configured to arrange image data received from an external part according to odd-th data ICs and even-th data ICs, and sequentially provide the odd-th and even-th arranged image data to the odd-th and even-th data ICs using a multi-drop scheme.

Abstract: An image display device and a method of driving the same, which reduce the number of transmission/reception lines of image data using a multi-drop intra-panel interface as well as to improve the bandwidth use efficiency. The image display device includes: an image display panel configured to display an image by including a plurality of pixel regions; a plurality of first gate integrated circuits (ICs) located at a first side of the image display panel so as to drive gate lines of the liquid crystal panel; a plurality of data integrated circuits (ICs) configured to drive data lines of the image display panel; and a timing controller configured to arrange image data received from an external part according to odd-th data ICs and even-th data ICs, and sequentially provide the odd-th and even-th arranged image data to the odd-th and even-th data ICs using a multi-drop scheme.

Abstract: A liquid crystal display device includes a liquid crystal panel including a plurality of gate lines (GL1 to GLn) data lines (DL1 to DLm) and a plurality of pixel areas; a timing controller arranging the external input image data to be proper to the driving of the liquid crystal panel, generating a gate control signal (GCS) and a data control signal (DCS), and grouping the arranged image data into a plurality of groups each having a plurality of controller channels, and outputting a group control signal (HINV_m) by determining whether the arranged image data for each group is proper to horzintal-1-dot inversion or horizontal-2-dot inversion; a gate driver driving the plurality of the gate lines of the liquid crystal panel based on the gate control signal (GCS) from the timing controller; and a data driver grouping output terminals into a plurality of groups.

Abstract: Disclosed is a display device. The display device includes a plurality of MCC packages each including one source driver IC and one gate driver IC disposed on a film, a panel including a plurality of data lines connected to the source driver IC, a plurality of gate connection lines that are connected to the gate driver IC and disposed in parallel to the data lines, a plurality of gate lines that are disposed vertically to the gate connection lines and the data lines and connected to the gate connection lines, and a plurality of dummy lines disposed in parallel to the gate connection lines and between the data lines, and a timing controller configured to transfer image data and a plurality of control signals to at least one or more of the MCC packages.

Abstract: An LCD device and a method of driving the same are provided. The LCD device includes a panel, one or more gate driver IC, a timing controller, and a source driver IC. The gate driver IC sequentially drives a plurality of gate lines formed in the panel. The timing controller controls the gate driver IC. The source driver IC simultaneously transfers image data from a first latch to a second latch according to a latch signal, converts the image data transferred from the second latch into data voltages, and outputs the data voltages to the panel at a falling time of a source output enable signal.

Abstract: A liquid crystal display device includes a liquid crystal panel including a plurality of gate lines (GL1 to GLn) data lines (DL1 to DLm) and a plurality of pixel areas; a timing controller arranging the external input image data to be proper to the driving of the liquid crystal panel, generating a gate control signal (GCS) and a data control signal (DCS), and grouping the arranged image data into a plurality of groups each having a plurality of controller channels, and outputting a group control signal (HINV_m) by determining whether the arranged image data for each group is proper to horzintal-1-dot inversion or horizontal-2-dot inversion; a gate driver driving the plurality of the gate lines of the liquid crystal panel based on the gate control signal (GCS) from the timing controller; and a data driver grouping output terminals into a plurality of groups.

Abstract: A self-refreshing SRAM with internal DRAM memory cells is provided with a test mode enable circuit for testing the real refresh time of the internal SRAM memory cells and for determining the maximum refresh capability of the internal DRAM memory cells. The self-refreshing DRAM includes a test-mode enable circuit, an arbitration circuit, and a memory control logic circuit. In a normal mode of operation, the test mode enable circuit is not active. In a test mode of operation, the test mode enable circuit is active which enables the memory control logic to be controlled by an external command signal that is provided through an external pin, such as a chip-enable /CE pin when the chip is in the test mode.

Abstract: Internally refreshing one or more DRAM arrays without requiring additional external command signals. Scheduling of either refresh cycles and/or read/write access cycles uses an arbitration and selection circuit that receives a refresh request input signal from an independent oscillator and a row access select RAS input signal. A wordline address multiplexer provides either internally-provided refresh or externally-provided row-line address signals to a wordline decoder. A refresh row counter uses a token status signal for activating only one refresh row counter at a time. Instantaneous refresh power is controlled by controlling the number of cells in each DRAM block. An arbitration and control system includes an address transition block with a delay for resolving metastability, a refresh control block, a RAS control block, and an arbitration circuit that temporarily stores unselected requests.

Abstract: A power-up control circuit has three components including a normal power-supply voltage level detection section, a special command section for detecting a deep-sleep enable input signal, and an output driver section that logically combines the output signal of the normal power-supply voltage level detection section and the special command detecting section to provide an improved, combined power-up control signal CPWRUP. The combined power-up control signal CPWRUP signal is temporarily brought to a LOW state for a predetermined period of time immediately after the end of a power-saving mode of operation, such as a deep-sleep mode of operation for a memory device. The LOW state of the combined power-up control signal CPWRUP output signal allows all internal circuitry to be returned to their initial states that are the same as those obtained after a normal power-up sequence, even though the external voltage level stays at its normal level.

Abstract: An improved voltage boosting circuit operates entirely from a single, common VCC voltage supply. An NMOS pass transistor has a gate input terminal to which is connected a gate boost capacitor and a PMOS precharge circuit. A drain terminal of the NMOS pass transistor is connected to a drain boost capacitor and to a drain precharge circuit. The gate boost capacitor is precharged from the common VCC voltage. The second terminal of the precharged gate boost capacitor is connected to the common VCC voltage level to thereby boost the precharged gate input terminal voltage to 2 VCC. The drain of the NMOS pass transistor has a similar boost capacitor and precharge configuration. Another embodiment further includes an additional gate preboost capacitor and a gate preboost precharge circuit for boosting the gate voltage to 3 VCC to more efficiently drive the NMOS pass transistor.

Abstract: Internally refreshing one or more DRAM arrays without requiring additional external command signals. Scheduling of either refresh cycles and/or read/write access cycles uses an arbitration and selection circuit that receives a refresh request input signal from an independent oscillator and a row access select RAS input signal. A wordline address multiplexer provides either internally-provided refresh or externally-provided row-line address signals to a wordline decoder. A refresh row counter uses a token status signal for activating only one refresh row counter at a time. Instantaneous refresh power is controlled by controlling the number of cells in each DRAM block. An arbitration and control system includes an address transition block with a delay for resolving metastability, a refresh control block, a RAS control block, and an arbitration circuit that temporarily stores unselected requests.

Abstract: A method and queuing circuit are provided for storing asynchronous external RAS access requests and for executing corresponding RAS cycles. When no current external access RAS cycle is currently underway a first request latch or similar storage element is set in response to an initial access request. When access to the memory begins in a RAS cycle, this first request latch is reset. When a RAS cycle is currently underway, a second request-queuing latch is set in response to a new, second access request that occurs. Whenever a RAS cycle is completed, if the second queuing latch is set, a new RAS cycle is initiated and both the first and the second latches are reset. Any subsequent new access request may then be queued if the subsequent new access request arrives prior to completion of the current second access cycle.

Abstract: A synchronous memory includes a column main-decoder circuit that is directly coupled to column select lines (CSL), and a timing controller that controls both enable timing and disable timing of the column select lines by controlling the column pre-decoder. The CSL timing controller generates a CSL timing control signal representative of the enable timing and the disable timing of the column select lines. The column pre-decoder is either enabled or disabled depending upon logic states of the CSL timing control signal. The timing controller includes a first control circuit which provides a CSL enable control signal, a CSL disable control circuit which provides a CSL disable control signal, and a flip-flop circuit which receives the CSL enable and disable control signals and provides the CSL timing control signal.

Abstract: A voltage boosting power supply circuit of a memory integrated circuit and a method for controlling charge amount of a voltage boosting power supply. The voltage boosting power supply circuit includes first and second power suppliers, first and second fuses, a voltage boosting controller, a voltage boosting enabling unit, and a voltage booster. The first and second power suppliers supply power supply. Each of one ends of the first and second fuses is connected to the first and second power suppliers. The voltage boosting controller generates first and second control signals a voltage boosting controller for generating first and second control signals, responding to a voltage boosting control signal which is in a ground voltage state before signals generated from each of other ends of the first and second fuses and the power supply become stable, and becomes logic high when the power supply becomes stable.

Abstract: A dynamic column redundancy driving circuit for a synchronous semiconductor memory device is provided. The circuit includes a first node, a precharging portion, an address determining portion, a clock delay portion, and a driving portion. The precharging portion precharges the first node in the first phase of the clock. The address determining portion is connected to the first node and includes a plurality of fuses selectively disconnected according to a defect address and changes a logic level of the first node in the second phase of the clock according to whether an address matches the defect address. The clock delay portion delays the clock. The driving portion receives the output of the address determining portion and the output of the clock delay portion and produces a redundancy wordline driving signal.

Abstract: A voltage detecting circuit and method in a synchronous DRAM is disclosed. The circuit includes first and second pull-up switching portion, first and second pull-down switching portion, first and second pull-up portion, first and second pull-down portion, ; switching transistor and a driving portion. The pull-up and pull-down switching portion are selectively turned-on according to a mode control signal, and the current paths are different for the active power down mode and the normal mode. Each pull-up portion includes a plurality of NMOS transistors connected in series and gated by the boosted voltage and each pull-down portion includes a plurality of NMOS transistors connected in series. An effective channel length of the current path selected in case of the active power down mode is longer than that selected in case of the normal operation mode.

Abstract: An input/output signal transmitting stylus includes an external case, a cylindrical body within the external case, a pickup rod partially within the cylindrical body and for outputting a signal, a transducer connected with the pickup rod for actuating a switching operation, a transducer operated by the transducer actuator, a circuit substrate for interfacing a signal input by the pickup rod, and spring within the cylindrical body and engaging the pickup rod enabling the pickup rod to reciprocate linearly within the external case and cylindrical body. The cylindrical body includes opposite front and rear walls and the pickup rod includes a disk disposed between the first and second walls so that the movement of the pickup rod is limited in two directions. Therefore, the pressure applied to the transducer is limited. The cylindrical body provides protection to the spring by preventing the intrusion of foreign matter extending the lifetime of the stylus.