Abstract: An input/output signal transmitting stylus includes an external case, a cylindrical body within the external case, a pickup rod partially within the cylindrical body and for outputting a signal, a transducer connected with the pickup rod for actuating a switching operation, a transducer operated by the transducer actuator, a circuit substrate for interfacing a signal input by the pickup rod, and spring within the cylindrical body and engaging the pickup rod enabling the pickup rod to reciprocate linearly within the external case and cylindrical body. The cylindrical body includes opposite front and rear walls and the pickup rod includes a disk disposed between the first and second walls so that the movement of the pickup rod is limited in two directions. Therefore, the pressure applied to the transducer is limited. The cylindrical body provides protection to the spring by preventing the intrusion of foreign matter extending the lifetime of the stylus.

Abstract: A MOS capacitor has uniform C-V capacitance characteristics across an operating voltage range and has reduced susceptibility to insulator breakdown and includes a semiconductor substrate of first conductivity type, a region of insulating material on an upper surface of the substrate and a well region of second conductivity type extending adjacent the region of insulating material. The well region is spaced from the region of insulating material so that the substrate extends to the upper surface therebetween. A source region of second conductivity type is formed in the well region. An insulating layer is formed on the source region and extends over the region of insulating material. A first electrode is formed on the insulating layer and a second electrode is formed on the source region. The capacitor also includes a P-N junction established between the source region of second conductivity type and the region of insulating material beneath the insulating layer.

Abstract: An integrated circuit provides a power supply voltage, a first boosted voltage, and a second boosted voltage which is preferably equal to or greater than the first boosted voltage, to the integrated circuit transistors, such that the integrated circuit transistors operate using the power supply voltage, the first boosted voltage and the second boosted voltage. The integrated circuit includes a first boosting circuit which boosts the power supply voltage to a first boosted voltage and a second boosting circuit which boosts the power supply voltage to a second boosted voltage. The first boosting circuit is preferably responsive to application of the power supply voltage to the integrated circuit and the second boosting circuit is preferably responsive to application of the power supply voltage to the integrated circuit and to an enable signal.

Abstract: A row redundancy circuit for use in a semiconductor memory device having one memory cell array, and first and second main row decoders and first and second spare row decoders formed on both sides of the memory cell array includes a first fuse box for receiving addresses and, during the occurrence of a defective address out of the received addresses, cutting a fuse on an input path of the defective address, thereby to supply an output signal to the first spare row decoder, a second fuse box for receiving addresses and, during the occurrence of a defective address out of the received addresses, cutting a fuse on an input path of the defective address, thereby to supply an output signal to the second spare row decoder, and a row redundancy control circuit for receiving the output signals of the first and second fuse boxes and selectively supplying an output signal responsive to the received input signal level to the first and second spare row decoders.

Abstract: A semiconductor memory device has adjacent memory arrays and isolation transistors disposed between a common bit sense amplifier and the memory arrays. An isolation control circuit according the present invention generates the power supply voltage Vcc (not the boost voltage Vpp) during the burn-in mode of operation, so that the gate oxide layer of the isolation transistors is prevented from being destroyed or deteriorated.

Abstract: Disclosed is a semiconductor device with redundancy for replacing a memory cell with a predetermined defect with additional spare cells. In a semiconductor memory device having a plurality of normal submemory arrays, the present invention discloses a redundancy technique that allows any redundant address decoder to be used with any of the submemory arrays. This maximizes efficiency in redundant repairs as well as maximizes the use of the chip area.