Abstract: A storage device may include a memory and a controller. The controller may input, to the memory, a read command for a first plane among the plurality of planes through a first path connected to the first terminal, receive, from the memory, read data for the read command through a second path connected to the second terminal, and input, to the memory, one or more additional commands through the first path in parallel with an operation of receiving the read data during an expected output time of the read data.

Abstract: A memory system comprises a memory device including a plurality of memory blocks, and a controller configured to manage a first count, a second count, and a sum value for each of the plurality of memory blocks, the first count being the number of performed random read operations, the second count being the number of performed sequential read operations, the sum value being calculated based on the first count and the second count, and configured to perform a read reclaim operation for a specific memory block among the plurality of memory blocks based on a comparison result of the sum value for the specific block with a reference value.

Abstract: A memory controller may include an external device interface configured to receive system configuration setting information from a first external device, a logical address feature map storage circuit configured to generate a logical address feature map by extracting, from the system configuration setting information, logical address feature data that defines a computational type for each logical address range specified by the first external device, a computational core configured to process write-requested data in a corresponding computational type, in response to a write request for a logical address included in the logical address feature map, and a memory interface configured to transmit the processed write data to a second external device.

Abstract: A suspend parameter determination device may include a power monitoring circuit configured to monitor power consumption information of a storage device; a memory device configured to store an artificial intelligence model; and a control circuit configured to load the artificial intelligence model, input to the artificial intelligence model, performance information for the storage device and the power consumption information received from the power monitoring circuit, and transmit, to the storage device, a suspend parameter outputted by the artificial intelligence model.

Abstract: A memory system comprises a memory device including a plurality of memory blocks, and a controller configured to manage a first count, a second count, and a sum value for each of the plurality of memory blocks, the first count being the number of performed random read operations, the second count being the number of performed sequential read operations, the sum value being calculated based on the first count and the second count, and configured to perform a read reclaim operation for a specific memory block among the plurality of memory blocks based on a comparison result of the sum value for the specific block with a reference value.

Abstract: A storage device includes a memory device and a controller. The memory device includes a plurality of memory regions. The controller is configured to perform a test operation on a target memory region among the memory regions when it is impossible to determine a second program standby time amount by which a second program operation remains as not performed on the target memory region after a first program operation is performed on the target memory region, and configured to control, according to a result of the test operation, the memory device to perform an adjusted second program operation on the target memory region.

Abstract: Embodiments of the disclosed technology relate to a memory system, a memory controller, and an operation method of the memory system. Based on embodiments of the disclosed technology, the memory system may suspend a target operation, which is a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. Accordingly, the memory system is capable of preventing a problem in that the end time of a program operation or an erase operation is excessively delayed, and controlling the number of times a program operation or an erase operation is suspended.

Abstract: A storage device may determine a target memory block from among a plurality of memory blocks, determine a target memory unit from among the plurality of memory units included in the target memory block, and program target dummy data into the target memory unit when it is determined that the target dummy data is not programmed into the target memory unit and when the program operation for the target memory unit is not yet completed.

Abstract: The present invention relates to sustained-release microspheres which include semaglutide or a pharmaceutically acceptable salt thereof, and a sustained-release formulation composition including the same, which enable long-term sustained release of a drug without an initial burst, and have no release delay (lag phase) while having excellent bioavailability.

Abstract: A side sill assembly for a vehicle includes a side sill inner, a side sill outer including an upper end portion and a lower end portion connected to the side sill inner, and a reinforcement member disposed between the side sill internal and the side sill outer in a longitudinal direction of the vehicle and fastened to the side sill internal further includes a side sill bracket mounted between the side sill outer and the reinforcement member and configured to support the side sill outer and the reinforcement member between the side sill outer and the reinforcement member to improve a stiffness against a side collision.

Abstract: A solar cell panel cleaning system according to an embodiment of the present invention includes a cleaning unit body configured to remove foreign substances attached to the solar cell panel, a driving force-providing unit configured to move the cleaning unit body, and a controller including a contamination region calculation unit configured to sense a contaminated region of the solar cell panel, and a wireless communication module configured to provide information on the contaminated region to the driving force-providing unit and the cleaning unit body.

Abstract: The present invention relates to a light emitting package. A light emitting package according to an embodiment of the present invention may include a body, a light emitting diode chip, and a light transmission member. The body includes a cavity open at an tipper side thereof and may be formed of a ceramic material. The light emitting diode chip is mounted in the cavity of the body and may generate and emit UV light. The light transmission member may be disposed on top of the body to cover the cavity. In addition, the light transmission member may include a light transmission layer formed of sapphire and a light loss prevention layer formed on at least one surface of the light transmission layer. The light loss prevention layer may include a lower light loss prevention layer formed on a lower surface of the light transmission layer. The light emitting diode chip and the light transmission member may be spaced apart from each other to form a space therebetween.

Abstract: A light emitting diode package is provided to include: a package substrate including a first substrate electrode and a second substrate electrode spaced apart from each other; a light emitting diode chip disposed on the package substrate to be electrically connected to the first substrate electrode and the second substrate electrode; and an encapsulant containing a fluorine compound and covering the light emitting diode chip to be at least partially in contact with the light emitting diode chip.

Abstract: A substrate transfer system capable of performing efficient distribution exchange between fabricating facilities is provided. The substrate transfer system includes a lower rail, an upper rail which is located above the lower rail from a ground plane, and extends to be parallel to the lower rail, a conveyor which extends to intersect the lower rail and the upper rail, below the lower rail, a first lower transport unit which transports a first carrier along the lower rail and unloads the first carrier onto the conveyor, and a first upper transport unit which transports a second carrier along the upper rail and unloads the second carrier onto the conveyor, wherein the conveyor includes a linear module which moves the first carrier and the second carrier in a linear direction, and a turning module which turns the first carrier and the second carrier.

Abstract: Disclosed is a light emitting diode package. According to one embodiment, the light emitting diode package includes a body and a light emitting diode chip. The body includes a substrate and a sidewall formed on the substrate and may be formed with a cavity therein. The light emitting diode chip may be mounted on the substrate in the cavity of the body. The sidewall may include multiple inner side surfaces formed to surround the cavity. The inner side surfaces of the sidewall may include adjacent inner side surfaces forming an angle of 90 degrees or more therebetween. In addition, the substrate may include an insulating base, a first interconnect pattern formed on the base, a second interconnect pattern spaced apart from the first interconnect pattern, and an insulating region disposed inside the cavity to separate the first interconnect pattern from the second interconnect pattern.

Abstract: An embodiment side reinforcement structure includes a first bracket coupled to a side sill and a second bracket inserted into and connected to a first side of the first bracket and coupled to a chassis frame. An embodiment vehicle includes a vehicle body including a chassis frame, a center pillar, a side sill, and floor lower member connected to the side sill and a side reinforcement structure including a first bracket coupled to the side sill and a second bracket inserted into and connected to a first side of the first bracket and coupled to the chassis frame.

Abstract: A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on to-be completed pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.

Abstract: A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on to-be completed pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.

Abstract: A storage device having enhanced operating efficiency includes a memory device with a plurality of memory blocks and a memory controller that performs an operation of de-randomizing data stored in different memory blocks using an identical random seed. The memory controller includes a random table that has a first address group including physical page addresses of a first memory block and a second address group including physical page addresses of a second memory block. The random table also has a random seed group that includes random seeds corresponding to the first address group and the second address group.

Abstract: Embodiments of the disclosed technology relate to a memory system, a memory controller, and an operation method of the memory system. Based on embodiments of the disclosed technology, the memory system may suspend a target operation, which is a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. Accordingly, the memory system is capable of preventing a problem in that the end time of a program operation or an erase operation is excessively delayed, and controlling the number of times a program operation or an erase operation is suspended.