Abstract: An apparatus for constructing a library for deriving a material composition using empirical result, which enables acceleration of research on the material-properties relationship. By applying the empirical results of the material composition, missing data of the material compositions can be statistically calculated by using supervised non-linear imputation techniques. The completed composition information of the materials is passed as an input of machine learning material-properties relationship prediction.

Abstract: A data storage device may include: a nonvolatile memory apparatus including a plurality of groups configured by dividing a plurality of planes in interleaving units; and a controller configured to check whether a group including a read region of a current read command is included in a group including a read operation of a previous read command and whether the read region of the current read command extends over two or more groups, when receiving the current read command, and control the nonvolatile memory apparatus to perform cache read or interleaving read based on the check result.

Abstract: A controller may include: a memory suitable for storing map data and unmap data; a counter suitable for counting a number of the unmap data stored in the memory; a setter suitable for setting offset values to each of the unmap data when the number of the unmap data is equal to or greater than a predetermined threshold value; and a compressor suitable for compressing the unmap data to have a predetermined compression length based on the offset values.

Abstract: The memory controller includes an unmap controller configured to receive unmap information from a host, calculate operation times required to perform a plurality of respective unmap operations based on the unmap information, and output an unmap command for an unmap operation having a relatively short operation time among the plurality of unmap operations as a result of the calculation; a buffer memory configured to store a plurality of types of address mapping information; and a control processor configured to control the unmap controller and the buffer memory in response to a command received from the host.

Abstract: Methods, systems and devices for efficiently performing a read fail recovery operation are described. An exemplary data storage device includes a nonvolatile memory device including a page group in which program-completed pages and program-in-progress pages are mixed, a buffer memory configured to buffer data and an XOR parity to be stored in pages of the page group. The data storage device also includes a recovery circuit configured to recover an error of read-failed data, and a processor configured to control the recovery circuit to read data and an XOR parity corresponding to the program-in-progress pages from the buffer memory. The processor is also configured to recover the error of the read-failed data using data corresponding to remaining program-completed pages other than a page in which the read-failed data is stored among the program-completed pages, and the data and the XOR parity read from the buffer memory.

Abstract: A memory controller capable of controlling a memory device to perform a fine program operation, based on a time elapsing from a foggy program completion time and a position of a page on which a fine program is performed controls the memory controller including a plurality of pages. The memory controller includes: a fine program timer for recording a time at which a foggy program completion response corresponding to a foggy program operation is received from the memory device, and outputting dummy program instruction information, based on a time elapsing from the recorded foggy program completion time; and a command controller for outputting a fine program command, based on the dummy program instruction information.

Abstract: A data storage device includes a nonvolatile memory device including one or more memory blocks having a first region and a second region and a controller configured to generate one or more write commands for writing data in the first region and the second region and transmit the one or more write commands to the nonvolatile memory device. The nonvolatile memory device includes a page buffer configured to store data to be written in the memory block and a control logic configured to control, based on the one or more write commands, the nonvolatile memory device to write the data in the first region and retain the data in the page buffer and to write the data retained in the page buffer in the second region.

Abstract: The memory controller includes a register allocator for dividing one super block into a plurality of unit areas, a plurality of first counters each corresponding to a respective one of the plurality of unit areas, wherein each of the plurality of first counters increments a count value when a corresponding unit area is read accessed, a second counter corresponding to the super block, wherein the second counter increments a count value when a count value of any of the first counters reaches a first threshold value, and a command generator for generating a command for performing a read reclaim operation when the count value of the second counter reaches a second threshold value.

Abstract: A storage device having enhanced operating efficiency may include: a memory device including a plurality of memory blocks; and a memory controller configured to perform, using an identical random seed, an operation of de-randomizing data stored in different memory blocks among the plurality of memory blocks.

Abstract: A memory system, a memory controller and a memory device are provided. The memory controller groups a first set of a plurality of memory blocks into a first super block, and a number of memory dies corresponding to the first super block is less than a number of memory dies corresponding to one channel and the number of memory dies corresponding to the first super block is determined differently depending on which of one or more control parameters are received by the memory controller. Through this, it is possible to provide a memory system, a memory controller and a memory device which can flexibly configure a super block while improving the performance of a read, program or erase operation for the super block.

Abstract: A controller includes: a command queue scheduler for queuing normal commands, and providing a priority order to a suspend command, when the suspend command is input; a data input/output component for outputting data in response to a data output signal output the command queue scheduler, and stopping the output of the data in response to a data output stop signal; and a data monitor for dividing data input to the data input/output component into a plurality of data groups, and monitoring information of a data group including data currently output from the data input/output component. The data input/output component outputs data up to the currently output data included in the data group and then stops the output of the data, in response to the data output stop signal. The command queue scheduler outputs the suspend command, when the output of the data group is stopped.

Abstract: The memory controller is provided to include: an operation controller configured to control memory devices to read first to third source pages and a source parity page in a source stripe and perform program operations on first to third target pages and a target parity page in a target stripe, a program data determiner configured to determine first to third program data to be programmed in the first to third target pages and to determine data read successfully from the first and second source pages as the first and second program data and determine recovery data as the third program data upon whether the read operation for the third source page has failed, and a parity calculator configured to generate calculation data by using the first and second program data, and generate the recovery data by using source parity data and the calculation data.

Abstract: A memory system, a memory controller and an operating method of the memory controller. The memory controller may include a host interface configured to communicate with a host; a memory interface configured to communicate with a memory device; and a control circuit configured to control an operation of the memory device. The control circuit may selectively determine to use a cache for an operation indicated by a command received from the host, depending on a number of memory dies, of a plurality of memory dies in the memory device, detected to be in an activated state.

Abstract: A data storage device includes: a non-volatile memory device, a random access memory and a processor. The non-volatile memory device stores a plurality of L2P entries related to a plurality of logical addresses. The random access memory stores a sequential flag table including sequential flags for a plurality of sequential segments. Each of the sequential flags are flags representing whether physical addresses corresponding to the logical addresses of the sequential segments are sequential or not. The processor identifies a sequential flag of a sequential segment related to read logical address information based on the sequential flag table. The processor reads at least one of the L2P entries, which are correspond to the read logical address information based on the sequential flag and loads the read L2P entry into the random access memory.

Abstract: A method for operating a memory system includes checking, by a memory device manager, an available capacity of a memory device in response to a write request transmitted from a host device; determining, by the memory device manager, a parallel access size based on the available capacity; comparing, by the memory device manager, a size of host data to be written in one or more nonvolatile memory devices in response to the write request, with the available capacity; receiving, by the memory device manager, host data of a first size in the memory device from the host device; and writing, by an access unit, the host data received in the memory device, to the nonvolatile memory devices by a unit of the parallel access size.

Abstract: A memory system includes a nonvolatile memory device; a random access memory configured to store, in response to an unmap request received from a host device, a flag information indicating that an unmap address as a target of the unmap request is unmapped; and a control unit configured to flush the flag information to the nonvolatile memory device, wherein the control unit flushes the flag information to the nonvolatile memory device when a first condition is satisfied.

Abstract: A memory system includes a plurality of memory devices, each including a plurality of memory blocks; and a controller configured to evaluate performance grades of the plurality of memory blocks, form super blocks spanning the plurality of memory devices by selecting memory blocks, among the plurality of memory blocks, to be included in each of the super blocks based on the performance grades, and write-access an opened super block, among the super blocks.

Abstract: Methods, systems and devices for efficiently performing a read fail recovery operation are described. An exemplary data storage device includes a nonvolatile memory device including a page group in which program-completed pages and program-in-progress pages are mixed, a buffer memory configured to buffer data and an XOR parity to be stored in pages of the page group. The data storage device also includes a recovery circuit configured to recover an error of read-failed data, and a processor configured to control the recovery circuit to read data and an XOR parity corresponding to the program-in-progress pages from the buffer memory. The processor is also configured to recover the error of the read-failed data using data corresponding to remaining program-completed pages other than a page in which the read-failed data is stored among the program-completed pages, and the data and the XOR parity read from the buffer memory.

Abstract: A memory system includes a nonvolatile memory device; a random access memory configured to store, in response to an unmap request received from a host device, a flag information indicating that an unmap address as a target of the unmap request is unmapped; and a control unit configured to flush the flag information to the nonvolatile memory device, wherein the control unit flushes the flag information to the nonvolatile memory device when a first condition is satisfied.

Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device includes a memory controller having a map manager and preload mapping information storage, and a memory device having logical-to-physical mapping information. The memory controller determines and obtains from the memory device, preloads mapping information, and then stores the preload mapping information in the preload mapping information storage, before a map update operation of the logical-to-physical mapping information is performed. The preload mapping information includes logical-to-physical mapping information to be updated.