Abstract: A memory system includes a memory medium including a plurality of matrices and a plurality of data input/output (I/O) terminals, a row address adding circuit configured to add row address additive values to an input row address for accessing memory cells of the plurality of matrices, and a column address adding circuit configured to add column address additive values to an input column address for accessing to memory cells of the plurality of matrices. The plurality of matrices are configured into a plurality of matrix sub-groups, wherein each matrix sub-group includes matrices accessed through the same data I/O terminal. The row address additive values are different from each other according to the matrix sub-groups, and the row address additive values are different from each other according to the matrix sub-groups.

Abstract: A data transmission system includes a data transmitter and a data receiver. The data transmitter outputs ‘N’-bit transmission data (where ‘N’ denotes a natural number which is equal to or greater than two). The data receiver receives the ‘N’-bit transmission data through ‘N’-number of data transmission lines. The data receiver transmits a re-transmission request signal to the data transmitter when the ‘N’-bit transmission data inputted to the data receiver are erroneous data. The data transmitter divides the ‘N’-bit transmission data in response to the re-transmission request signal and operates in a first data re-transmission mode so that the divided transmission data are resent, together with first ground data, to the data receiver.

Abstract: A data processing system is disclosed, which relates to a technology for implementing a convergence memory system provided with a plurality of memories. The data processing system includes a compute blade configured to generate a write command to store data and a read command to read the data, and a memory blade configured to selectively performed read and write operations in response to the read and write commands in a plurality of memories. The compute blade has a memory that stores information about performance characteristics of each of the plurality of memories, and is configured to determine priority information through which eviction of a cache line is carried out based on the stored information.

Abstract: A memory controller may include an address control block. The address control block may be configured to remap a write target address when a number of write data having a first logic level is within a correctable range and when a level of a datum corresponding to the write target address has the first logic level.

Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.

Abstract: A memory system may include: a memory device having a plurality of banks, each comprising a memory cell region including a plurality of memory cells, and a page buffer unit; and a controller suitable for receiving a write address and write data from a host, and controlling a write operation of the memory device, wherein the controller comprises: a page buffer table (PBT) comprising fields to retain the same data as the page buffer units of the respective banks; and a processor suitable for comparing the write data to data stored in a field of the PBT, corresponding to the write address, and controlling the memory device to write the write data or the data stored in the page buffer unit to memory cells selected according to the write address, based on a comparison result.

Abstract: A cache system includes a cache memory having a plurality of blocks, a dirty line list storing status information of a predetermined number of dirty lines among dirty lines in the plurality of blocks, and a cache controller controlling a data caching operation of the cache memory and providing statuses and variation of statuses of the dirty lines, according to the data caching operation, to the dirty line list. The cache controller performs a control operation to always store status information of a least-recently-used (LRU) dirty line into a predetermined storage location of the dirty line list.

Abstract: A memory system includes a memory device including a plurality of memory blocks, a first detection block suitable for detecting a hot memory block based on a number of times that a write operation is performed among the memory blocks during the write operation, a second detection block suitable for detecting first memory blocks based on the number of times that the write operation is performed among the memory blocks and detecting a cold memory block based on addresses of the first memory blocks, when the hot memory block is detected, and a wear-leveling block suitable for swapping data of the hot memory block for data of the cold memory block.

Abstract: A cache memory includes a first cache area corresponding to even addresses, and a second cache area corresponding to odd addresses, wherein each of the first and second cache areas includes a plurality of cache sets, and each cache set includes a data set field suitable for storing data corresponding to an address among the even and odd addresses, and a pair field suitable for storing information on a location where data corresponding to an adjacent address which is adjacent to an address corresponding to the stored data is stored.

Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.

Abstract: A memory system may include a nonvolatile memory device and a wear leveling unit. The nonvolatile memory device includes a plurality of memory blocks. The wear leveling unit may be configured to intermittently increase an accumulative access count of a memory block among the memory blocks by a predetermined value, decide a wear level of the memory block based on the accumulative access count whenever the accumulative access count is increased, set the memory block to a hot block based on the wear level, and perform a hot block management operation on the hot block. The wear leveling unit may increase the accumulative access count in response to an access count reaching a predetermined value. The accumulative access count may be stored in the nonvolatile memory device, and the access count may be stored in a volatile memory device.

Abstract: A memory module includes a first memory device that includes first circuit nodes for communication with a memory controller and second circuit nodes for communication inside the memory module, a second memory device that includes first circuit nodes for communication with the memory controller and second circuit nodes for communication inside the memory module, and an internal data bus that couples the first memory device to the second memory device to carry data between the second circuit nodes of the first memory device and the second circuit nodes of the second memory device. When an internal read command is applied to the first memory device and an internal write command is applied to the second memory device, data is transferred from the first memory device to the second memory device through the internal data bus.

Abstract: A memory device includes a memory region; and an access unit suitable for setting an offset value according to control of an external device, changing, in response to an access command of the external device for a first address of the memory region, the first address into a second address of the memory region based on the offset value, and performing an access operation for the second address.

Abstract: A data processing system includes a compute blade generating a write command to store data and a read command to read the data, and a memory blade. The compute blade has a memory that stores information about performance characteristics of each of a plurality of memories, and determines priority information through which eviction of a cache line is carried out based on the stored information.

Abstract: A semiconductor system may include a memory device and a controller. The memory device may include a plurality of decks. Each of the decks may include word lines and bit lines alternately stacked. The controller may control an operation for data of the decks included in the memory device. The controller may include a counting circuit block for counting access numbers of the word lines and the bit lines. The counting circuit block may include a plurality of x-counting blocks corresponding to the word lines that are stacked a plurality of y-counting blocks corresponding to the bit lines that are stacked. The x-counting blocks may count access numbers of selected word lines in accordance with a selection signal of a corresponding deck among the decks. The y-counting block may count access numbers of selected bit lines in accordance with the selection signal of the corresponding deck.

Abstract: A memory system includes a memory device and a memory controller. The memory device has a plurality of memory regions. The memory controller is configured to generate a read command for a first memory region corresponding to one of the plurality of memory regions when the number of write commands successively generated for the first memory region reaches a reference value.

Abstract: A data processing system is disclosed, which relates to a technology for implementing a convergence memory system provided with a plurality of memories. The data processing system includes a compute blade configured to generate a write command to store data and a read command to read the data, and a memory blade configured to selectively performed read and write operations in response to the read and write commands in a plurality of memories. The compute blade has a memory that stores information about performance characteristics of each of the plurality of memories, and is configured to determine priority information through which eviction of a cache line is carried out based on the stored information.

Abstract: A memory system includes a host controller and a cache system. The host controller includes a host queue in which host data including a command outputted from a host are stored. The cache system includes a cache memory having a plurality of sets and a cache controller controlling an operation of the cache memory. The cache controller transmits status information on a certain set to which the host data are to be transmitted among the plurality of sets to the host controller. The host controller receives the status information from the cache controller to determine transmission or non-transmission of the host data stored in the host queue to the cache system.

Abstract: A memory system includes a memory device comprising first to Nth memory regions, wherein N is a natural number equal to or more than 2, and a memory controller suitable for checking numbers of first logic level data which are contained in first to Nth data groups to be written to the memory device, respectively, and writing the first to Nth data groups to the first to Nth memory regions in order based on the checked numbers.

Abstract: A memory device includes a plurality of memory regions including memory cells coupled between a plurality of word lines and a plurality of bit lines, an address decoder suitable for decoding an address to generate a plurality of selection signals corresponding to the bit lines, and outputting the selection signals to a plurality of signal lines, and a plurality of selection circuits corresponding to the memory regions, respectively, and suitable for selecting the bit lines in response to the selection signals received through the signal lines, wherein at least one of the selection circuits is coupled to the signal lines in an arrangement different from remaining selection circuits.