Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.

Abstract: A memory system may include: a memory device having a plurality of banks, each comprising a memory cell region including a plurality of memory cells, and a page buffer unit; and a controller suitable for receiving a write address and write data from a host, and controlling a write operation of the memory device, wherein the controller comprises: a page buffer table (PBT) comprising fields to retain the same data as the page buffer units of the respective banks; and a processor suitable for comparing the write data to data stored in a field of the PBT, corresponding to the write address, and controlling the memory device to write the write data or the data stored in the page buffer unit to memory cells selected according to the write address, based on a comparison result.

Abstract: An error correcting method of a memory system may include: reading read data and an error correction code from a plurality of memory chips; correcting an error of the read data using the error correction code; temporarily storing the read data and the error correction code in a buffer when the correcting of the error fails; writing a certain input test pattern in the plurality of memory chips, reading an output test pattern written in the plurality of memory chips, and detecting a fail chip in which a chipkill occurs; recorrecting, based on a location of the detected fall chip, the error of the read data stored in the buffer using the error correction code stored in the buffer; and rewriting error-corrected read data and the error correction code in the plurality of memory chips.

Abstract: Disclosed is an address mapping method of a memory system. The address mapping method may include grouping adjacent memory cells into multiple cubes, from a plurality of memory cells respectively located at intersections of a plurality of row lines and a plurality of column lines; allocating most significant bit (MSB) N bits of a physical address for identifying the cubes; allocating least significant bit (LSB) M bits of the physical address for designating locations of memory cells included in each of the cubes, M and N being positive integers; storing information about a mapping between a logical address and the (M+N)-bit physical address in a mapping table; and when the logical address in response to an external request is received, translating the logical address to the physical address based on the mapping table.

Abstract: Disclosed is an address mapping method of a memory system. The address mapping method may include grouping adjacent memory cells into multiple cubes, from a plurality of memory cells respectively located at intersections of a plurality of row lines and a plurality of column lines; allocating most significant bit (MSB) N bits of a physical address for identifying the cubes; allocating least significant bit (LSB) M bits of the physical address for designating locations of memory cells included in each of the cubes, M and N being positive integers; storing information about a mapping between a logical address and the (M+N)-bit physical address in a mapping table; and when the logical address in response to an external request is received, translating the logical address to the physical address based on the mapping table.