Patents by Inventor Seung Ho Pyi

Seung Ho Pyi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10559587
    Abstract: A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Ji Yeon Baek, Seung Ho Pyi
  • Patent number: 10367001
    Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: July 30, 2019
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Publication number: 20190221582
    Abstract: A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.
    Type: Application
    Filed: March 27, 2019
    Publication date: July 18, 2019
    Applicant: SK hynix Inc.
    Inventors: Ki Hong LEE, Seung Ho PYI, In Su PARK
  • Publication number: 20190221581
    Abstract: A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.
    Type: Application
    Filed: March 25, 2019
    Publication date: July 18, 2019
    Inventors: Ki Hong LEE, Seung Ho PYI, Seung Jun LEE
  • Patent number: 10347653
    Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit 5 insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: July 9, 2019
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Publication number: 20190206892
    Abstract: A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Inventors: Ki Hong LEE, Ji Yeon BAEK, Seung Ho PYI
  • Patent number: 10290651
    Abstract: A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 14, 2019
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, In Su Park
  • Patent number: 10283518
    Abstract: A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: May 7, 2019
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seung Jun Lee
  • Patent number: 10269827
    Abstract: A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 23, 2019
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Ji Yeon Baek, Seung Ho Pyi
  • Publication number: 20190088677
    Abstract: A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 21, 2019
    Inventors: Ki Hong Lee, Seung Ho Pyi, Il Young Kwon, Jin Ho Bin
  • Publication number: 20180342533
    Abstract: A semiconductor device includes a cell structure; n first pad structures formed on one side of the cell structure and each configured to have a step form in which 2n layers form one stage; and n second pad structures formed on the other side of the cell structure each configured to have a step form in which 2n layers form one stage, wherein n is a natural number of 1 or higher, and the first pad structures and the second pad structures have asymmetrical step forms having different heights.
    Type: Application
    Filed: July 17, 2018
    Publication date: November 29, 2018
    Applicant: SK hynix Inc.
    Inventors: Ki Hong LEE, Seung Ho PYI, Sung Ik MOON
  • Patent number: 10096617
    Abstract: A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Il Young Kwon, Jin Ho Bin
  • Patent number: 10096614
    Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: October 9, 2018
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 10096615
    Abstract: A semiconductor device includes a cell structure; n first pad structures formed on one side of the cell structure and each configured to have a step form in which 2n layers form one stage; and n second pad structures formed on the other side of the cell structure each configured to have a step form in which 2n layers form one stage, wherein n is a natural number of 1 or higher, and the first pad structures and the second pad structures have asymmetrical step forms having different heights.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: October 9, 2018
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Sung Ik Moon
  • Publication number: 20180254285
    Abstract: A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.
    Type: Application
    Filed: May 3, 2018
    Publication date: September 6, 2018
    Inventors: Ki Hong LEE, Ji Yeon BAEK, Seung Ho PYI
  • Publication number: 20180240813
    Abstract: A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.
    Type: Application
    Filed: April 13, 2018
    Publication date: August 23, 2018
    Applicant: SK hynix Inc.
    Inventors: Ki Hong LEE, Seung Ho PYI, Seok Min JEON
  • Publication number: 20180219023
    Abstract: A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.
    Type: Application
    Filed: March 27, 2018
    Publication date: August 2, 2018
    Applicant: SK hynix Inc.
    Inventors: Ki Hong LEE, Seung Ho PYI, In Su PARK
  • Patent number: 9991279
    Abstract: A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: June 5, 2018
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Ji Yeon Baek, Seung Ho Pyi
  • Patent number: 9966384
    Abstract: A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: May 8, 2018
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, In Su Park
  • Patent number: 9941291
    Abstract: A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: April 10, 2018
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Il Do Kim