Patents by Inventor Seung Ho Pyi

Seung Ho Pyi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE
    Publication number: 20160035732
    Abstract: A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit.
    Type: Application
    Filed: October 9, 2015
    Publication date: February 4, 2016
    Inventors: Ki Hong LEE, Seung Ho PYI, Il Do KIM
  • three dimensional semiconductor device
    Publication number: 20160005747
    Abstract: A semiconductor device includes alternately stacked conductive layers and the insulating layers, an opening passing through the conductive layers and insulating layers, a first semiconductor layer formed in the opening, a second semiconductor layer formed in the first semiconductor layer, a capping layer formed in the opening and disposed over the first semiconductor layer and the second semiconductor layer, and a liner layer interposed between the first semiconductor layer and the second semiconductor layer and protruding through the capping layer relative to the first semiconductor layer and the second semiconductor layer.
    Type: Application
    Filed: December 5, 2014
    Publication date: January 7, 2016
    Inventors: Ki Hong LEE, Seung Ho PYI, In Su PARK
  • Double-source semiconductor device
    Patent number: 9224752
    Abstract: A semiconductor device may include a first source layer, a first insulating layer located over the first source layer, and a first stacked structure located over the first insulating layer. The semiconductor device may include first channel layers passing through the first stacked structure and the first insulating layer. The semiconductor device may include a second source layer including a first region interposed between the first source layer and the first insulating layer and a second region interposed between the first channel layers and the first insulating layer.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: December 29, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Ji Yeon Baek
  • Three dimensional semiconductor device including pads
    Patent number: 9202780
    Abstract: A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: December 1, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Semiconductor device and method of manufacturing the same
    Patent number: 9202870
    Abstract: A semiconductor device includes first conductive layers and first interlayer insulating layers stacked alternately with each other, at least one second conductive layer and at least one second interlayer insulating layer formed on the first conductive layers and the first interlayer insulating layers and stacked alternately with each other, a first semiconductor layer passing through the first conductive layers and the first interlayer insulating layers and including polysilicon, and a second semiconductor layer coupled to the first semiconductor layer and passing through the at least one second conductive layer the at least one second interlayer insulating layer, wherein the second semiconductor layer includes silicon germanium.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: December 1, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Jin Ho Bin
  • Three-dimensional structured memory devices
    Patent number: 9190416
    Abstract: In various embodiments, a three-dimensional structured nonvolatile semiconductor memory devices and methods for manufacturing the devices are disclosed. One such device includes an n-type doped region at a source/drain region; a p-type doped region at the source/drain region; and a diffusion barrier material between the n-type doped region and the p-type doped region. The n-type doped region is substantially isolated from the p-type doped region. Other embodiments are also disclosed.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: November 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, II Young Kwon, Jin Ho Bin
  • Three-dimensional non-volatile memory device
    Patent number: 9190514
    Abstract: A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: November 17, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Il Do Kim
  • SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150303211
    Abstract: A semiconductor device includes a semiconductor pattern; conductive layers each including a first portion through which the semiconductor pattern passes and a second portion having a thickness greater than the first portion, wherein the first portion of each conductive layer includes a first barrier pattern surrounding the semiconductor pattern and a material pattern, which is formed in the first barrier pattern and has an etch selectivity with respect to the first barrier pattern, and the second portion of each conductive layer includes a conductive pattern; and contact plugs connected to the second portion of each of the conductive layers.
    Type: Application
    Filed: September 8, 2014
    Publication date: October 22, 2015
    Inventors: Ki Hong LEE, Seung Ho PYI, Jin Ho BIN
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150294981
    Abstract: A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity.
    Type: Application
    Filed: June 25, 2015
    Publication date: October 15, 2015
    Inventors: Ki Hong LEE, Seung Ho PYI, Hyun Soo SHON
  • Non-volatile memory device and method for fabricating the same
    Patent number: 9159570
    Abstract: A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: October 13, 2015
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Dong-Sun Sheen, Seung-Ho Pyi, Sung-Jin Whang
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150279938
    Abstract: A semiconductor device includes first conductive layers and first interlayer insulating layers stacked alternately with each other, at least one second conductive layer and at least one second interlayer insulating layer formed on the first conductive layers and the first interlayer insulating layers and stacked alternately with each other, a first semiconductor layer passing through the first conductive layers and the first interlayer insulating layers and including polysilicon, and a second semiconductor layer coupled to the first semiconductor layer and passing through the at least one second conductive layer the at least one second interlayer insulating layer, wherein the second semiconductor layer includes silicon germanium.
    Type: Application
    Filed: June 16, 2015
    Publication date: October 1, 2015
    Inventors: Ki Hong LEE, Seung Ho PYI, Jin Ho BIN
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20150255385
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes insulating layers stacked in the shape of stairs, and conductive layers alternately stacked with the insulating layers, wherein the conductive layers each include a first region interposed between upper and lower insulating layers thereof, among the insulating layers, and a second region which extends from the first region and protrudes between the upper and lower insulating layers, and wherein a protruding part formed on a sidewall or an upper surface of the second region.
    Type: Application
    Filed: August 21, 2014
    Publication date: September 10, 2015
    Inventors: Ki Hong LEE, Seung Ho PYI, Seok Min JEON
  • Semiconductor device and method of manufacturing the same
    Patent number: 9123580
    Abstract: A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 1, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Hyun Soo Shon
  • TRANSISTOR, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150236112
    Abstract: A semiconductor device including a central region, side regions located in both sides of the central region, and conductive layers including a first barrier pattern formed in the central region, a material pattern formed in the first barrier pattern and having an etch selectivity with respect to the first barrier pattern, and a second barrier pattern formed in the material pattern; and insulating layers alternately stacked with the conductive layers.
    Type: Application
    Filed: July 7, 2014
    Publication date: August 20, 2015
    Inventors: Ki Hong LEE, Jin Ho BIN, Soo Jin KIM, Seung Ho PYI
  • Semiconductor device and method of manufacturing the same
    Patent number: 9099566
    Abstract: A semiconductor device includes a trench formed in a substrate, a first stacked structure formed in the trench and including a plurality of first material layers and a plurality of second material layers stacked alternately on top of each other, and a transistor located on the substrate at a height corresponding to a top surface of the first stacked structure.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: August 4, 2015
    Assignee: SK hynix Inc.
    Inventors: Oh Chul Kwon, Ki Hong Lee, Seung Ho Pyi
  • Semiconductor device and method of manufacturing the same
    Patent number: 9099348
    Abstract: A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: August 4, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Hyun Soo Shon
  • Semiconductor device and method of manufacturing the same
    Patent number: 9087735
    Abstract: A semiconductor device includes first conductive layers and first interlayer insulating layers stacked alternately with each other, at least one second conductive layer and at least one second interlayer insulating layer formed on the first conductive layers and the first interlayer insulating layers and stacked alternately with each other, a first semiconductor layer passing through the first conductive layers and the first interlayer insulating layers and including polysilicon, and a second semiconductor layer coupled to the first semiconductor layer and passing through the at least one second conductive layer the at least one second interlayer insulating layer, wherein the second semiconductor layer includes silicon germanium.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 21, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Jin Ho Bin
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150179564
    Abstract: A semiconductor device includes a stacked structure having first conductive layers stacked stepwise and first insulating layers interposed between the first conductive layers, wherein undercuts are formed under the first conductive layers and each of the first conductive layers includes a first region covered by the first conductive layer and a second region extending from the first region, contact pads coupled to the second regions of the respective first conductive layers, and a liner layer formed on the contact pads and filling the undercuts.
    Type: Application
    Filed: May 28, 2014
    Publication date: June 25, 2015
    Applicant: SK hynix Inc.
    Inventors: Ki Hong LEE, Seung Ho PYI, Ji Yeon BAEK
  • SEMICONDUCTOR MEMORY DEVICE INCLUDING A SLIT
    Publication number: 20150162345
    Abstract: A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.
    Type: Application
    Filed: February 17, 2015
    Publication date: June 11, 2015
    Applicant: SK hynix Inc.
    Inventors: Ki Hong LEE, Seung Ho PYI, In Su PARK
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150162342
    Abstract: A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.
    Type: Application
    Filed: May 20, 2014
    Publication date: June 11, 2015
    Applicant: SK hynix Inc.
    Inventors: Ki Hong LEE, Seung Ho PYI, Seung Jun LEE