Abstract: A display device, includes: a display area and a non-display area; a plurality of signal lines over the display area; and a plurality of connection lines in the display area and connected to the signal lines, wherein the plurality of connection lines includes a plurality of first connection lines connected to the signal lines, respectively, a plurality of third connection lines on a same layer as the first connection lines, and a plurality of second connection lines connecting the first connection lines to the third connection lines.

Abstract: A shoes care device includes an inner cabinet configured to accommodate shoes inside; a outlet configured to suck air inside the inner cabinet; a nozzle duct having one end hinge-coupled to the inner cabinet so as to protrude into the inner cabinet, and which forms a passage for air; a nozzle hinge-coupled to the other end of the nozzle duct so that the shoes can be inserted into the inner cabinet, and configured to inject air into the shoes; a nozzle connector, of which one end is hinge-coupled to the inner cabinet and of which the other end is hinge-coupled to the nozzle; a connection path from the suction to the nozzle; a blowing part in the connection path and configured to ventilate air from the outlet to the nozzle; and a dehumidifying part in the connection path and capable of dehumidifying the ventilated air.

Abstract: A low profile flat bombe for Liquefied Petroleum Gas (LPG) storage and method for manufacturing the same, may include a flat bombe body including an upper plate having a plurality of first piercing holes and a pump installation hole formed therethrough, a lower plate having a plurality of second piercing holes formed therethrough at positions vertically coinciding with the plurality of first piercing holes, and side plates integrally connecting first and second side end portions of the upper and lower plates, end plates mounted at front and rear openings in the flat bombe body, and support pipes, wherein upper end portions of the support pipes are welded to internal circumferential portions of the plurality of first piercing holes and lower end portions thereof are welded to internal circumferential portions of the plurality of second piercing holes to maintain a vertical distance between the upper and lower plates.

Abstract: An embodiment resin composition for shielding electromagnetic waves, based on a total weight of the resin composition, includes 20 to 80 wt % of thermoplastic resin, 1 to 50 wt % of a conductive filler, and 0.1 to 30 wt % of an additive.

Abstract: A shoes care device includes an inner cabinet having an accommodation space configured to accommodate shoes; a outlet formed on a bottom of the inner cabinet so as to suck air inside the inner cabinet; a connection path forming a flow path through which air in the accommodation space is discharged from the inner cabinet through the outlet and then introduced back into the accommodation space; a blowing part disposed in the connection path and configured to ventilate air; a dehumidifying part disposed in the connection path and configured to dehumidify air; and a main shelf installed to cover the bottom of the inner cabinet and having an upper surface on which the shoes can be settled.

Abstract: Disclosed are various methods for transmitting or receiving data or control information having high reliability conditions. A method for operating a terminal which transmits uplink control information (UCI) includes: a step of generating UCI; a step of comparing the priority of an uplink (UL) control channel for the transmission of the UCI with the priority of a UL data channel when some symbols of the UL control channel and the UL data channel overlap; and a step of selecting the UL channel having a higher priority among the UL control channel and the UL data channel, and transmitting the UCI to a base station through the selected UL channel.

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a vertical field-effect transistor (VFET) that includes a bottom source/drain region in a substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, and a gate structure on a side of the channel region. The channel region may have a cross-shaped upper surface.

Abstract: A vertical field-effect transistor (VFET) includes: a fin structure on a substrate; a gate structure including a gate dielectric layer on an upper portion of a sidewall of the fin structure, and a conductor layer on a lower portion of the gate dielectric layer; a top source/drain (S/D) region above the fin structure and the gate structure; a bottom S/D region below the fin structure and the gate structure; a top spacer on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.

Abstract: Integrated circuit devices including standard cells are provided. The standard cells may include a first vertical field effect transistor (VFET) including a first channel region and having a first conductivity type and a second VFET including a second channel region and having a second conductivity type that is different from the first conductivity type. Each of the first channel region and the second channel region may extend longitudinally in a first horizontal direction, and the first channel region may be spaced apart from the second channel region in a second horizontal direction that is perpendicular to the first horizontal direction.

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Abstract: A device inserted into a living body to generate an anticancer material is disclosed. The disclosed device comprises: an electric energy converter which receives an external signal to convert the external signal into electric energy; at least one electrode pair for causing electrolysis in a body fluid inside the living body by using the electric energy converted by the electric energy converter; and a light emitter for emitting light at a by-product produced by means of electrolysis by using the electric energy converted by the electric energy converter.

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

Abstract: A cell architecture and a method for placing a plurality of cells to form the cell architecture are provided. The cell architecture includes at least a 1st cell and a 2nd cell placed next to each other in a cell width direction, wherein the 1st cell includes a one-fin connector which is formed around a fin among a plurality of fins of the 1st cell, and connects a vertical field-effect transistor (VFET) of the 1st cell to a power rail of the 1st cell, wherein a 2nd cell includes a connector connected to a power rail of the 2nd cell, wherein the fin of the 1st cell and the connector of the 2nd cell are placed next to each other in the cell width direction in the cell architecture, and wherein the one-fin connector of the 1st cell and the connector of the 2nd cell are merged.

Abstract: A cell architecture and a method for placing a plurality of cells to form the cell architecture are provided. The cell architecture includes at least a 1st cell and a 2nd cell placed next to each other in a cell width direction, wherein the 1st cell includes a one-fin connector which is formed around a fin among a plurality of fins of the 1st cell, and connects a vertical field-effect transistor (VFET) of the 1st cell to a power rail of the 1st cell, wherein a 2nd cell includes a connector connected to a power rail of the 2nd cell, wherein the fin of the 1st cell and the connector of the 2nd cell are placed next to each other in the cell width direction in the cell architecture, and wherein the one-fin connector of the 1st cell and the connector of the 2nd cell are merged.

Abstract: An image of a space in which a mobile robot travels may be captured, and, in the case in which personal information is included in the captured image, the image including the personal information may be covered with a specific color such that the personal information is not visible, and the image may be replaced with an image including no personal information. As a result, it is possible to prevent the personal information from being exposed. In order to determine whether personal information is included in an image and to replace the image including the personal information with an image including no personal information, an object detection neural network and a frame prediction neural network may be used. In addition, input and output of an image may be performed in an Internet of Things (IoT) environment using a 5G network.

Abstract: A vertical field-effect transistor (VFET) device and a method of manufacturing the same are provided. The VFET device includes: a fin structure formed on a substrate; a gate structure including a gate dielectric layer formed on an upper portion of a sidewall of the fin structure, and a conductor layer formed on a lower portion of the gate dielectric layer; a top source/drain (S/D) region formed above the fin structure and the gate structure; a bottom S/D region formed below the fin structure and the gate structure; a top spacer formed on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer formed between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.

Abstract: A method for manufacturing a fin structure of a vertical field effect transistor (VFET) includes: (a) patterning a lower layer and an upper layer, deposited on the lower layer, to form two patterns extended in two perpendicular directions, respectively; (b) forming a first spacer and a second spacer side by side in the two patterns along sidewalls of the lower layer and the upper layer exposed through the patterning; (c) removing the first spacer, the second spacer and the upper layer above a level of a top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed through the two patterns in the plan view; (d) removing the lower layer, the upper layer, and the second spacer remaining on the substrate after operation (c); and (e) etching the substrate downward except a portion thereof below the first spacer remaining on the substrate after operation (d), and removing the remaining first spacer, thereby to obtain the fin structure.

Abstract: A method for manufacturing a fin structure for a vertical field effect transistor (VFET) includes: forming on a substrate mandrels having at least one first gap therebetween; forming first spacers on side surfaces of the mandrels such that at least one second gap, smaller than the first gap, is formed between the first spacers; forming a second spacer on side surfaces of the first spacers; removing the mandrels and the first spacers to leave the second spacer on the side surfaces of the first spacers; removing the second spacer, on the side surfaces of the first spacers, at a predetermined portion so that the remaining second spacer has a same two-dimensional (2D) shape as the fin structure; and removing a portion of the substrate, except below the remaining second spacer, and the remaining second spacer so that the substrate below the remaining second spacer forms the fin structure.

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a vertical field-effect transistor (VFET) that includes a bottom source/drain region in a substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, and a gate structure on a side of the channel region. The channel region may have a cross-shaped upper surface.