Abstract: The present invention suggests a substrate manufacturing method and a manufacturing method of a semiconductor device comprising: providing a SOI structure having an insulation layer and a silicon layer laminated on a substrate; laminating to form a silicon germanium layer and a capping silicon layer on the SOI structure; implementing oxidation process at two or more temperatures and heat treatment process at least once during the oxidation process to form a germanium cohesion layer and a silicon dioxide layer; and removing the silicon dioxide layer.

Abstract: Disclosed are a novel oxazolidinone derivative exhibiting inhibitory activity against CETP, a preparation method thereof, and a pharmaceutical composition comprising the same. Exhibiting excellent inhibitory activity against CETP, the oxazolidinone derivative can be effectively applied to the prevention or treatment of various CETP enzyme activity- or HDL cholesterol level-related diseases such as dyslipidemia, atherosclerosis, and coronary heart disease.

Abstract: Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region

Abstract: A voltage measurement device is provided. The voltage measurement device includes a contact portion configured to contact an electric wire for transmitting an alternating current (AC) voltage and to output an induced voltage induced by the AC voltage in a surface of the electric wire, a capacitive element connected in series to the contact portion, and a controller configured to calculate amplitude of the AC voltage using the induced voltage output from the contact portion and a second voltage output from the capacitive element.

Abstract: Disclosed are a novel oxazolidinone derivative exhibiting inhibitory activity against CETP, a preparation method thereof, and a pharmaceutical composition comprising the same. Exhibiting excellent inhibitory activity against CETP, the oxazolidinone derivative can be effectively applied to the prevention or treatment of various CETP enzyme activity- or HDL cholesterol level-related diseases such as dyslipidemia, atherosclerosis, and coronary heart disease.

Abstract: Integrated circuit device with transistors having different threshold voltages and methods of forming the device are provided. The device may include the first, second and third transistors having threshold voltages different from each other. The first transistor may be free of a stacking fault and the second transistor may include a stacking fault. The concentration of the channel implant region of the third transistor may be different from the concentration of the channel implant region of the first transistor.

Abstract: Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region

Abstract: An image sensor and an operating method thereof are disclosed. The image sensor includes a first photoelectric conversion portion configured to receive plural lights, except for a light of first wavelength, to generate an electric charge; and a second photoelectric conversion portion configured to receive the light of the first wavelength to generate an electric charge, wherein at least a portion of the first photoelectric conversion portion and the second photoelectric conversion portion is spaced apart from each other in a vertical direction.

Abstract: An implantable pressure sensor arrangement is disclosed. The arrangement includes a substrate, a coil positioned on the substrate, a flexible membrane positioned proximate to the coil and configured to be moveable with respect to the coil, thereby forming a fluid chamber, fluidly sealed from outside of the implantable pressure sensor arrangement, a porous membrane positioned on the flexible membrane and configured to transfer pressure from outside of the implantable pressure sensor arrangement onto the flexible membrane wherein a differential pressure is generated on the two sides of the flexible membrane thereby causing the flexible membrane to deflect towards and away from the coil, and an electrode coupled to the flexible membrane.

Abstract: Integrated circuit device with transistors having different threshold voltages and methods of forming the device are provided. The device may include the first, second and third transistors having threshold voltages different from each other. The first transistor may be free of a stacking fault and the second transistor may include a stacking fault. The concentration of the channel implant region of the third transistor may be different from the concentration of the channel implant region of the first transistor.

Abstract: A method of correcting errors includes receiving a codeword including main data and parity data stored in a memory cell array to perform an error check and correction (ECC) decoding on the codeword and selectively performing an error correction on the codeword based on a result of the ECC decoding using asymmetry of error occurrence of the main data.

Abstract: A clothes treatment apparatus (100) and a control method thereof are disclosed. The clothes treatment apparatus (100) includes a cabinet (1) closed by a door (3) and an accommodation space (2) provided in the cabinet (1), consisting for example of a first accommodation space (21) and a second accommodation space (23), wherein a 5t mechanism chamber (25) is provided. The clothes treatment apparatus (100) includes a fixed nozzle device (4) comprising heated air supply holes (41), steam supply holes (43) and detergent supply holes (45) and a moving nozzle device (5) which reciprocates along a guide part (51). Clothes are held by a hanger (7) in the accommodation space (2).