Patents by Inventor Seung-Jin Seo
Seung-Jin Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240129648Abstract: An image sensing device includes: a control circuit coupled between an output terminal of a pixel signal and a high voltage terminal, and configured to generate a control voltage corresponding to a voltage level of the pixel signal; and a current supplying circuit coupled between the output terminal and the high voltage terminal, and configured to supply a pre-charge current, which is configured to be adaptively adjusted according to the voltage level of the pixel signal, to the output terminal based on the control voltage.Type: ApplicationFiled: December 21, 2023Publication date: April 18, 2024Inventors: Yu Jin PARK, Nam Ryeol KIM, Kang Bong SEO, Jeong Eun SONG, Jung Soon SHIN, Seung Hwan LEE
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Publication number: 20240119949Abstract: An encoding/decoding apparatus and method for controlling a channel signal is disclosed, wherein the encoding apparatus may include an encoder to encode an object signal, a channel signal, and rendering information for the channel signal, and a bit stream generator to generate, as a bit stream, the encoded object signal, the encoded channel signal, and the encoded rendering information for the channel signal.Type: ApplicationFiled: November 30, 2023Publication date: April 11, 2024Applicant: Electronics and Telecommunications Research InstituteInventors: Jeong Il SEO, Seung Kwon BEACK, Dae Young JANG, Kyeong Ok KANG, Tae Jin PARK, Yong Ju LEE, Keun Woo CHOI, Jin Woong KIM
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Publication number: 20240076468Abstract: An embodiment resin composition for shielding electromagnetic waves, based on a total weight of the resin composition, includes 20 to 80 wt % of thermoplastic resin, 1 to 50 wt % of a conductive filler, and 0.1 to 30 wt % of an additive.Type: ApplicationFiled: January 16, 2023Publication date: March 7, 2024Inventors: Seung-Woo Choi, Dong-Bum Seo, Kyun Oh, Yu-Hyun Song, Yang-Jin Kwon, Joo-Han Lee
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Publication number: 20240075853Abstract: An apparatus of tilting a seat cushion of a vehicle, includes a tilting motor, a pinion gear, a sector gear, and a tilting link which perform the tilting operation of the seat cushion and exert a binding force in a tilted state of the seat cushion and are provided to be connected to both of one side and the other side of a seat cushion frame, and has two sector gears positioned on left and right sides and connected to each other by a connection bar so that, by strengthening a binding force of the front portion of the seat cushion, it is possible to secure the safety of passengers in the event of a collision.Type: ApplicationFiled: April 13, 2023Publication date: March 7, 2024Applicants: Hyundai Motor Company, Kia Corporation, DAS CO., LTD, Faurecia Korea, Ltd., Hyundai Transys Inc.Inventors: Sang Soo LEE, Mu Young KIM, Sang Hark LEE, Ho Suk JUNG, Sang Do PARK, Chan Ho JUNG, Dong Hoon LEE, Hea Yoon KANG, Deok Soo LIM, Seung Pil JANG, Seon Ho KIM, Jong Seok YUN, Hyo Jin KIM, Dong Gyu SHIN, Jin Ho SEO, Young Jun KIM, Taek Jun NAM
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Patent number: 9320147Abstract: A semiconductor module assembly is provided. The semiconductor module assembly includes a motherboard, a socket, and a semiconductor module. The motherboard includes an opening for receiving the semiconductor module, the opening including at least three sides. The socket is disposed in the opening along at least a first side, second side, and third side of the at least three sides. The semiconductor module is disposed in the socket. The semiconductor module includes at least one semiconductor device mounted on a module board. The socket includes at least a first side along the first side of the opening, and a second side along the second side of the opening, and the semiconductor module electrically connects to the motherboard through at least the first and second sides of the socket.Type: GrantFiled: January 31, 2013Date of Patent: April 19, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong-Hyeon Cho, Jae-Jun Lee, Jung-Joon Lee, Baek Kyu Choi, Seung-Jin Seo
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Patent number: 8576637Abstract: A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on a first chip selecting signal, a second chip selecting signal, a row address signal, a column address signal, and a write enable signal. The mode selecting circuit selects one of a parallel test mode and a mode register control mode in response to the mode control signal.Type: GrantFiled: December 3, 2010Date of Patent: November 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Soon-Deok Jang, Seok-Il Kim, Seung-Jin Seo, You-Keun Han
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Publication number: 20130279916Abstract: Embodiments disclose a server system including a first circuit board which includes a first socket connected to a memory controller via an electrical channel; and a second circuit board which is combined with the first socket such that signals are exchanged with the memory controller via at least one of the electrical channel and an optical channel. The optical channel is combined with the electrical channel via an electrical-to-optical conversion device, the electrical-to-optical conversion device converts an electrical signal into an optical signal or converts an optical signal into an electrical signal.Type: ApplicationFiled: February 14, 2013Publication date: October 24, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong-hyeon CHO, You-keun HAN, Seung-jin SEO, Jung-joon LEE, Kyoung-ho HA
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Patent number: 8462534Abstract: A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.Type: GrantFiled: March 27, 2012Date of Patent: June 11, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Il Kim, You-Keun Han, Seung-Jin Seo
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Patent number: 8261301Abstract: A broadcast receiver and a method for managing reserved recording information are disclosed. If a cell for a reserved recording list is added to an EPG (Electronic Program Guide), a user can easily check, modify, or delete all information associated with the reserved recording on the EPG, such that the user can conveniently manage the reserved recording information on the EPG. A method for managing reserved recording information of a broadcast receiver includes the steps of: a) receiving a reserved recording signal of a specific program; b) storing reserved recording information of the program on the basis of the reserved recording signal; and c) loading the stored reserved recording information, inserting the loaded reserved recording information into a pre-stored Electronic Program Guide (EPG), and creating an EPG-reserved recording list.Type: GrantFiled: August 24, 2006Date of Patent: September 4, 2012Assignee: LG Electronics Inc.Inventors: Sung Suk Kang, Seung Jin Seo
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Publication number: 20120218703Abstract: A circuit board assembly includes a first circuit board having an electrical connection circuit on a surface thereof. A second circuit board is on the surface of the first circuit board. A first memory socket is mounted on the second circuit board. The first memory socket is only electrically connected to the electrical connection circuit through the second circuit board. A second memory socket is mounted on the second circuit board. The second memory socket that is only electrically connected to the electrical connection circuit through the second circuit board.Type: ApplicationFiled: September 22, 2011Publication date: August 30, 2012Inventors: Jeong Hyeon Cho, Myung Hee Sung, Kyoung Sun Kim, Seung Jin Seo, Jung Joon Lee
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Publication number: 20120182777Abstract: A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.Type: ApplicationFiled: March 27, 2012Publication date: July 19, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-Il KIM, You-Keun HAN, Seung-Jin SEO
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Patent number: 8159853Abstract: A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.Type: GrantFiled: January 25, 2010Date of Patent: April 17, 2012Assignee: Samsung Electronis Co., Ltd.Inventors: Seok-Il Kim, You-Keun Han, Seung-Jin Seo
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Patent number: 8051343Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.Type: GrantFiled: October 22, 2010Date of Patent: November 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
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Publication number: 20110176371Abstract: A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on a first chip selecting signal, a second chip selecting signal, a row address signal, a column address signal, and a write enable signal. The mode selecting circuit selects one of a parallel test mode and a mode register control mode in response to the mode control signal.Type: ApplicationFiled: December 3, 2010Publication date: July 21, 2011Inventors: Soon-Deok Jang, Seok-Il Kim, Seung-Jin Seo, You-Keun Han
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Patent number: 7965530Abstract: A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.Type: GrantFiled: December 8, 2008Date of Patent: June 21, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: You-Keun Han, Seung-Jin Seo, Kwan-Yong Jin, Jung-Hwan Choi, Jong-Hoon Kim, Seok-Il Kim, Joo-Sun Choi
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Publication number: 20110113296Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.Type: ApplicationFiled: October 22, 2010Publication date: May 12, 2011Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
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Patent number: 7930465Abstract: A semiconductor memory device capable of determining an operation mode by using states of data pins, and an operation mode determining method for the same are disclosed. The semiconductor memory device includes at least one MRS input pad, at least one data input pad, and an operation mode determining circuit. The operation mode determining circuit generates an operation mode determining signal, when an MRS command input through the MRS input pad corresponds to a predetermined MRS command and data signals input through the data input pad or pads include a predetermined combination. Accordingly, the efficiency in the manufacturing and producing processes may be improved by determining the operation mode of the semiconductor memory device in a module assembly process.Type: GrantFiled: October 21, 2005Date of Patent: April 19, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Il Kim, Young-Man Ahn, Byung-Se So, Seung-Jin Seo
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Patent number: 7849373Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.Type: GrantFiled: September 30, 2008Date of Patent: December 7, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
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Publication number: 20100202180Abstract: A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.Type: ApplicationFiled: January 25, 2010Publication date: August 12, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-Il KIM, You-Keun HAN, Seung-Jin SEO
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Publication number: 20100169725Abstract: a memory module test system for testing a plurality of memory modules includes a plurality buffers in one-to-one correspondence the plurality of memory modules, each of the buffers including a self-test engine for testing a corresponding memory module. The test system further includes an interface configured to receive a test program for testing the memory module, and a gate array configured to transmit the test program to the buffers using a Joint Test Action Group (JTAG) protocol and to read test results of the test program from the buffers using the JTAG protocol.Type: ApplicationFiled: December 29, 2009Publication date: July 1, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Kuk Lee, Seung Hee Mun, Seung Jin Seo, Woo-Jin Na