Abstract: A mask read-only memory (ROM) includes parallel doping lines of a second conductivity type formed in a substrate of a first conductivity type, a first insulation film formed on the doping lines and the substrate, conductive pads fainted on the first insulation film, a second insulation film formed on the first insulation film and the conductive pads, parallel wires formed on the second insulation film extending perpendicular to the doping lines, contact plugs formed in the first insulation film that connect the doping lines to the conductive pads, and vias formed in the second insulation film that connect the conductive pads to the wires, wherein crossings of the doping lines and the wires define memory cells, contact plugs and vias are formed in memory cells of a first type, and at least one of the contact plug and via are missing from memory cells of a second type.

Abstract: Disclosed herein is a plate-shaped secondary battery constructed in a structure in which an electrode assembly of a cathode/separator/anode structure is mounted in a battery case, and the battery case is sealed by thermal welding, wherein the secondary battery has at least one valve (one-way exhaust valve), having a small thickness, mounted at a sealed portion, formed at the outer circumference of an electrode assembly receiving part of the battery case, for allowing internal high-pressure gas to be exhausted out of a battery cell and preventing external gas from being introduced into the battery cell. The secondary battery according to the present invention has the effect of effectively exhausting internal high-pressure gas generated during the abnormal operation of the battery, such as overcharge, out of the battery case, while maintaining the sealability of the battery case, thereby simultaneously improving the efficiency and safety of the battery.

Abstract: A method of programming a nonvolatile semiconductor memory device using a negative bias voltage. The method includes turning ON the string selection transistors connected to selected bit lines and turning OFF the string selection transistors connected to unselected bit lines in the same memory block, in a program mode. This can be achieved by applying a negative bias voltage to a bulk substrate and applying a voltage having a voltage level higher than the threshold voltage of string selection transistors connected to selected bit lines and lower than the threshold voltage of string selection transistors connected to unselected bit lines. The method may reduce programming disturbance between a selected cell string and an unselected cell string.

Abstract: Provided is a semiconductor device for applying common source lines with individual bias voltages. The device includes a substrate, cell transistors arrayed in a cell matrix shape on the substrate and configured to have gate insulating patterns, gate electrodes, common source regions, drain regions and channel regions. Word lines are configured to electrically interconnect the gate electrodes with each other. Common source lines are shared between only a pair of the neighboring word lines and are configured to electrically interconnect the common source regions with each other. Drain metal contacts and source metal contacts are arranged in a straight line on the drain regions. Bit lines are electrically connected to the drain metal contacts. And impurity regions are configured to control the threshold voltage of the channel regions.

Abstract: A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via.

Abstract: Disclosed herein are an electrode assembly including a plurality of unit cells folded by a continuous separation film wherein the unit cells are arranged on the separation film such that electrode taps of the unit cells face each other, the separation film has openings corresponding to the electrode taps of the unit cells, and the electrode assembly is manufactured by folding the unit cells in the longitudinal (lengthwise) direction of the separation film while the unit cells are disposed such that the electrode taps of the unit cells are inserted into the corresponding openings, and an electrochemical cell, such as a secondary battery, including the same. The electrode assembly according to the present invention is a hybrid type electrode assembly solving the problems of the jelly-roll type electrode assembly and the stacking type electrode assembly.

Abstract: According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate.

Abstract: Disclosed are pairs of semiconductor flash memory cells including first and second source lines formed in a semiconductor substrate, semiconductor pillars extending from the substrate between the source lines, first and second charge storage structures formed on opposite side surfaces of the semiconductor pillar and separated by trench isolation structures. The x and y pitch separating adjacent semiconductor pillars in the memory cell array are selected whereby forming the trench isolation structures serves to separate both charge storage structures and conductive structures provided on opposite sides of a semiconductor pillars. Also disclosed are methods of fabricating such structures whereby the density of flash memory devices, particularly NOR flash memory devices, can be improved.

Abstract: Disclosed herein is a plate-shaped secondary battery constructed in a structure in which an electrode assembly of a cathode/separator/anode structure is mounted in a battery case, and the battery case is sealed by thermal welding, wherein the secondary battery has at least one valve (one-way exhaust valve), having a small thickness, mounted at a sealed portion, formed at the outer circumference of an electrode assembly receiving part of the battery case, for allowing internal high-pressure gas to be exhausted out of a battery cell and preventing external gas from being introduced into the battery cell. The secondary battery according to the present invention has the effect of effectively exhausting internal high-pressure gas generated during the abnormal operation of the battery, such as overcharge, out of the battery case, while maintaining the sealability of the battery case, thereby simultaneously improving the efficiency and safety of the battery.

Abstract: Disclosed is a photosensitive resin composition suitable for use in a transflective liquid crystal display (LCD). The photosensitive resin composition uses, as an alkali-soluble binder resin, a blend of two kinds of binder resins. The first binder resin has a weight average molecular weight greater than or equal to 1,000 but lower than 20,000 and contains no reactive group. The second binder resin has a weight average molecular weight greater than or equal to 20,000 but lower than 80,000 and contains reactive groups. The photosensitive resin composition has good adhesion to an underlying substrate while forming a high resolution fine pattern.

Abstract: A non-volatile memory device includes a memory cell array with a plurality of unit memory cells arranged in a matrix pattern, each of the unit memory cells having first and second non-volatile memory transistors sharing a common source, and a selection transistor connected between the common source and one of the first and second non-volatile memory transistors, a first word line coupled to control gates of the first non-volatile memory transistors arranged in a column direction of the memory cell array, a second word line coupled to control gates of the second non-volatile memory transistors arranged in the column direction of the memory cell array, a selection line coupled to gates of the selected transistors arranged in the column direction of the memory cell array, and at least one bit line coupled to drains of the first and second non-volatile memory transistors.

Abstract: A mobile terminal including a wireless communication unit configured to access a web page, a display unit configured to display the accessed web page, a receiving unit configured to receive input voice information, and a controller configured to convert the input voice information into text information, to search the displayed web page for objects that include the converted text information, and to control the display unit to distinctively display found objects that include the converted text information from other information displayed on the web page.

Abstract: Disclosed herein is a battery module including at least one battery cell constructed in a structure in which an electrode assembly of a cathode/separator/anode structure is mounted in a battery case such that electrode leads of the electrode assembly protrude outside, wherein, when external impacts are directly or indirectly applied to the battery cell, with the result that the electrode leads move toward the electrode assembly of the battery cell, the external impacts are absorbed by the deformation of the electrode leads or the deformation of predetermined regions (‘electrode lead facing parts’) of the module in direct contact with or adjacent to the electrode leads, whereby the occurrence of a short circuit due to the contact between the electrode assembly and the electrode leads is prevented.

Abstract: Disclosed herein is a secondary battery including an electrode assembly of a cathode/separator/anode structure mounted in a pouch-shaped battery case in a sealed state, wherein a residue portion, which is not sealed (non-sealing residue portion), is defined between a sealing portion of the battery case and the electrode assembly for collecting generated gas, and the non-sealing residue portion is formed by mounting the electrode assembly between upper and lower laminate sheets, at least one of which has a receiving part of a size approximately corresponding to the electrode assembly, sealing three sides of the upper and lower laminate sheets, including two sides where electrode terminals are disposed, among four sides of the upper and lower laminate sheets, injecting an electrolyte in the battery case through the non-sealing portion, and sealing the non-sealing portion such that the resultant sealing portion is spaced a predetermined width from the receiving part.

Abstract: A bonding pad having an anti-pad peeling-off structure is disclosed. In a method of forming the bonding pad, after a metal pad layer is formed, a slit is formed in the metal pad layer. A protecting layer is formed on the metal pad layer. The protecting layer is partially removed to expose the metal pad such that a portion of the protecting layer remains in the slits to be connected to the main protecting layer. The protecting layer formed in the slit is connected to the protecting layer such that the residual protecting layer pattern buffer when physical impacts are generated, to prevent peeling-off of the metal pad layer.

Abstract: a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

Abstract: A semiconductor device includes a tunnel insulation layer pattern, a charge trapping layer pattern, a blocking layer pattern and a gate structure. The tunnel insulation layer pattern is formed on a substrate. The charge trapping layer pattern is formed on the tunnel insulation layer pattern. The blocking layer pattern is formed on the substrate and extends up onto and covers the charge trapping layer pattern. The gate surrounds an upper portion of the charge trapping layer pattern so as to face towards and upper surface and opposite side surfaces of the charge trapping layer pattern.

Abstract: A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess.

Abstract: A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate on the semiconductor body, an inter-insulating layer on the memory device, and a conductive layer on the inter-insulating layer, and a memory device formed on the conductive layer including, a semiconductor body elongated in one direction having a cross section perpendicular to a main surface, having a predetermined curvature, a channel

Abstract: In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.