Abstract: According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate.

Abstract: A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via.

Abstract: A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface of the substrate and elongated direction, the cross section having a predetermined curvature, a channel region partially formed along the circumference of the semiconductor body, a tunneling insulating layer disposed on the channel region, a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region, an intergate insulating layer disposed on the floating gate, a control gate disposed on the intergate insulating layer and electrically insulated from the floating gate, and source and drain regions which are aligned with both sides of the control gate and formed within the semiconductor body.

Abstract: Disclosed are pairs of semiconductor flash memory cells including first and second source lines formed in a semiconductor substrate, semiconductor pillars extending from the substrate between the source lines, first and second charge storage structures formed on opposite side surfaces of the semiconductor pillar and separated by trench isolation structures. The x and y pitch separating adjacent semiconductor pillars in the memory cell array are selected whereby forming the trench isolation structures serves to separate both charge storage structures and conductive structures provided on opposite sides of a semiconductor pillars. Also disclosed are methods of fabricating such structures whereby the density of flash memory devices, particularly NOR flash memory devices, can be improved.

Abstract: A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess.

Abstract: Disclosed herein is a secondary battery constructed in a structure in which an electrode assembly having a cathode/separator/anode arrangement is mounted in a battery case made of a laminate sheet including a resin layer and a metal layer, electrode taps of the electrode assembly are coupled to corresponding electrode leads, and the electrode assembly is sealed in the battery case while electrode leads are exposed to the outside of the battery case, wherein a protective film is attached to coupling regions between the electrode taps and the electrode leads for sealing the coupling regions between the electrode taps and the electrode leads. The secondary battery according to the present invention is constructed in a structure in which the coupling regions are sealed by the protective film, unlike a conventional secondary battery constructed in a structure in which the coupling regions between the electrode taps and the electrode leads are exposed in the battery case.

Abstract: a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

Abstract: A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate on the semiconductor body, an inter-insulating layer on the memory device, and a conductive layer on the inter-insulating layer, and a memory device formed on the conductive layer including, a semiconductor body elongated in one direction having a cross section perpendicular to a main surface, having a predetermined curvature, a channel

Abstract: A mask read only memory (ROM) device includes a plurality of isolation patterns disposed at predetermined regions of a semiconductor substrate to define a plurality of active regions. The semiconductor substrate includes a mask ROM region where a plurality of on cells and a plurality of off-cells are disposed. The mask ROM further includes a plurality of gate lines disposed over the active regions, and which cross over the isolation patterns, a plurality of gate insulating layers interposed between the gate lines and the active regions and a floating conductive pattern and a inter-gate dielectric pattern located between the gate line and the gate insulating layer of the off-cell.

Abstract: Disclosed herein are an electrode assembly including a plurality of unit cells folded by a continuous separation film wherein the unit cells are arranged on the separation film such that electrode taps of the unit cells face each other, the separation film has openings corresponding to the electrode taps of the unit cells, and the electrode assembly is manufactured by folding the unit cells in the longitudinal (lengthwise) direction of the separation film while the unit cells are disposed such that the electrode taps of the unit cells are inserted into the corresponding openings, and an electrochemical cell, such as a secondary battery, including the same. The electrode assembly according to the present invention is a hybrid type electrode assembly solving the problems of the jelly-roll type electrode assembly and the stacking type electrode assembly.

Abstract: In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell and a method of forming the same are disclosed. The SONOS memory cell includes a substrate in which a recessed region having at least one side wall is arranged and a trap storage pattern with which the recessed region is filled with a first insulating film is interposed. A control gate electrode is arranged on the top surface of the substrate and the top surface of the trap storage pattern with a second insulating film interposed. First and second source/drain regions are arranged in the substrate on both sides of the control gate electrode. The top surface of the trap storage pattern is flat and is at least as high as the top surface of the substrate.

Abstract: A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface of the substrate and elongated direction, the cross section having a predetermined curvature, a channel region partially formed along the circumference of the semiconductor body, a tunneling insulating layer disposed on the channel region, a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region, an intergate insulating layer disposed on the floating gate, a control gate disposed on the intergate insulating layer and electrically insulated from the floating gate, and source and drain regions which are aligned with both sides of the control gate and formed within the semiconductor body.