Patents by Inventor Seung-Jin Yeom

Seung-Jin Yeom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9871045
    Abstract: A semiconductor device includes first conductive patterns adjacent to each other and isolated by a trench including first and second trenches, a second conductive pattern formed in the first trench, and an insulating pattern partially filling the second trench under the second conductive pattern and formed between the first conductive patterns and the second conductive pattern.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: January 16, 2018
    Assignee: HYNIX SEMICONDUCTOR INC.
    Inventors: Seung-Jin Yeom, Noh-Jung Kwak, Chang-Heon Park, Sun-Hwan Hwang
  • Patent number: 9698097
    Abstract: A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: July 4, 2017
    Assignee: SK Hynix Inc.
    Inventors: Nam-Yeal Lee, Seung-Jin Yeom
  • Patent number: 9514980
    Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming a sacrificial spacer over sidewalls of the open portion; forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion; forming an ohmic contact layer over the first conductive pattern; forming an air gap by removing the sacrificial spacer; capping the air gap by forming a barrier layer over the ohmic contact layer; and forming a second conductive pattern over the barrier layer to fill an upper section of the open portion.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: December 6, 2016
    Assignee: SK Hynix Inc.
    Inventors: Hyo-Seok Lee, Seung-Jin Yeom, Sung-Won Lim, Seung-Hee Hong, Nam-Yeal Lee
  • Patent number: 9466603
    Abstract: A semiconductor device includes a plurality of first conductive structures formed over a substrate, second conductive structures each formed between neighboring first conductive structures of the first conductive structures, air gaps each formed between the second conductive structures and the neighboring first conductive structures thereof, third conductive structures each capping a portion of the air gaps, and capping structures each capping the other portion of the air gaps.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: October 11, 2016
    Assignee: SK Hynix Inc.
    Inventors: Seung-Jin Yeom, Sung-Won Lim, Seung-Hee Hong, Hyo-Seok Lee, Nam-Yeal Lee
  • Publication number: 20160247760
    Abstract: A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap.
    Type: Application
    Filed: May 5, 2016
    Publication date: August 25, 2016
    Inventors: Nam-Yeal LEE, Seung-Jin YEOM
  • Patent number: 9373681
    Abstract: A method for fabricating a capacitor of a semiconductor device includes forming a mold layer over a substrate, forming a plurality of preliminary openings by selectively etching the mold layer, forming a plurality of openings where each opening is formed to have a given linewidth by forming a sacrificial layer on sidewalls of the preliminary openings, and forming a plurality of storage nodes in the plurality of openings.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: June 21, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Won Lim, Seung-Jin Yeom, Hyo-Seok Lee
  • Publication number: 20160172304
    Abstract: This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures, The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers over sidewalis of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs.
    Type: Application
    Filed: February 12, 2016
    Publication date: June 16, 2016
    Inventors: Nam-Yeal LEE, Seung-Jin YEOM, Sung-Won LIM, Seung-Hee HONG, Hyo-Seok LEE, Dong-Seok KIM, Seung-Bum KIM, Se-Jin KIM
  • Patent number: 9355903
    Abstract: A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: May 31, 2016
    Assignee: SK Hynix Inc.
    Inventors: Nam-Yeal Lee, Seung-Jin Yeom
  • Patent number: 9337202
    Abstract: A semiconductor device includes a first conductive structure including a first conductive pattern that is formed over a substrate, a second conductive structure formed adjacent to a sidewall of the first conductive structure, and an insulation structure including an air gap that is formed between the first conductive structure and the second conductive structure, wherein the second conductive structure includes a second conductive pattern, an ohmic contact layer that is to formed over the second conductive pattern, and a third conductive pattern that is formed over the ohmic contact layer and is separated from the first conductive pattern through the air gap.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: May 10, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Won Lim, Seung-Jin Yeom, Hyo-Seok Lee
  • Publication number: 20160104764
    Abstract: A method for fabricating a capacitor of a semiconductor device includes forming a mold layer over a substrate, forming a plurality of preliminary openings by selectively etching the mold layer, forming a plurality of openings where each opening is formed to have a given linewidth by forming a sacrificial layer on sidewalls of the preliminary openings, and forming a plurality of storage nodes in the plurality of openings.
    Type: Application
    Filed: December 11, 2015
    Publication date: April 14, 2016
    Inventors: Sung-Won LIM, Seung-Jin YEOM, Hyo-Seok LEE
  • Patent number: 9312210
    Abstract: A method for fabricating a semiconductor device includes forming, over a substrate, a plurality of first conductive structures which are separated from one another; forming multi-layered dielectric patterns including a first dielectric layer which covers upper ends and both sidewalls of the first conductive structures; removing portions of the first dielectric layer starting from lower end portions of the first conductive structures to define air gaps, and forming second conductive structures which are filled between the first conductive structures.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: April 12, 2016
    Assignee: SK Hynix Inc.
    Inventors: Hyo-Seok Lee, Seung-Jin Yeom
  • Patent number: 9293362
    Abstract: This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures. The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers over sidewalls of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 22, 2016
    Assignee: SK Hynix Inc.
    Inventors: Nam-Yeal Lee, Seung-Jin Yeom, Sung-Won Lim, Seung-Hee Hong, Hyo-Seok Lee, Dong-Seok Kim, Seung-Bum Kim, Sei-Jin Kim
  • Publication number: 20160049409
    Abstract: A semiconductor device includes a plurality of first conductive structures formed over a substrate, second conductive structures each formed between neighboring first conductive structures of the first conductive structures, air gaps each formed between the second conductive structures and the neighboring first conductive structures thereof, third conductive structures each capping a portion of the air gaps, and capping structures each capping the other portion of the air gaps.
    Type: Application
    Filed: October 27, 2015
    Publication date: February 18, 2016
    Inventors: Seung-Jin YEOM, Sung-Won LIM, Seung-Hee HONG, Hyo-Seok LEE, Nam-Yeal LEE
  • Patent number: 9245946
    Abstract: A method for fabricating a semiconductor device includes defining a curved active region by forming a plurality of trenches over a semiconductor substrate, forming an insulating layer to fill the plurality of trenches, and forming a pair of gate lines crossing the curved active region, so that it is possible to prevent leaning of an active region by forming a curved active region.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: January 26, 2016
    Assignee: SK Hynix Inc.
    Inventors: Hyo-Seok Lee, Seung-Jin Yeom, Sung-Won Lim
  • Patent number: 9240442
    Abstract: A method for fabricating a capacitor of a semiconductor device includes forming a mold layer over a substrate, forming a plurality of preliminary openings by selectively etching the mold layer, forming a plurality of openings where each opening is formed to have a given linewidth by forming a sacrificial layer on sidewalls of the preliminary openings, and forming a plurality of storage nodes in the plurality of openings.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: January 19, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Won Lim, Seung-Jin Yeom, Hyo-Seok Lee
  • Publication number: 20160005743
    Abstract: A semiconductor device includes a first conductive structure including a first conductive pattern that is formed over a substrate, a second conductive structure formed adjacent to a sidewall of the first conductive structure, and an insulation structure including an air gap that is formed between the first conductive structure and the second conductive structure, wherein the second conductive structure includes a second conductive pattern, an ohmic contact layer that is to formed over the second conductive pattern, and a third conductive pattern that is formed over the ohmic contact layer and is separated from the first conductive pattern through the air gap.
    Type: Application
    Filed: September 17, 2015
    Publication date: January 7, 2016
    Inventors: Sung-Won LIM, Seung-Jin YEOM, Hyo-Seok LEE
  • Publication number: 20150371891
    Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming a sacrificial spacer over sidewalls of the open portion; forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion; forming an ohmic contact layer over the first conductive pattern; forming an air gap by removing the sacrificial spacer; capping the air gap by forming a barrier layer over the ohmic contact layer; and forming a second conductive pattern over the barrier layer to fill an upper section of the open portion.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 24, 2015
    Inventors: Hyo-Seok LEE, Seung-Jin YEOM, Sung-Won LIM, Seung-Hee HONG, Nam-Yeal LEE
  • Patent number: 9214467
    Abstract: A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: December 15, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jin-Hyock Kim, Seung-Jin Yeom, Ki-Seon Park, Han-Sang Song, Deok-Sin Kil, Jae-Sung Roh
  • Patent number: 9202774
    Abstract: A semiconductor device includes a plurality of first conductive structures formed over a substrate, second conductive structures each formed between neighboring first conductive structures of the first conductive structures, air gaps each formed between the second conductive structures and the neighboring first conductive structures thereof, third conductive structures each capping a portion of the air gaps, and capping structures each capping the other portion of the air gaps.
    Type: Grant
    Filed: December 15, 2013
    Date of Patent: December 1, 2015
    Assignee: SK Hynix Inc.
    Inventors: Seung-Jin Yeom, Sung-Won Lim, Seung-Hee Hong, Hyo-Seok Lee, Nam-Yeal Lee
  • Patent number: 9165859
    Abstract: A semiconductor device includes a first conductive structure including a first conductive pattern that is formed over a substrate, a second conductive structure formed adjacent to a sidewall of the first conductive structure, and an insulation structure including an air gap that is formed between the first conductive structure and the second conductive structure, wherein the second conductive structure includes a second conductive pattern, an ohmic contact layer that is formed over the second conductive pattern, and a third conductive pattern that is formed over the ohmic contact layer and is separated from the first conductive pattern through the air gap.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: October 20, 2015
    Assignee: SK Hynix Inc.
    Inventors: Sung-Won Lim, Seung-Jin Yeom, Hyo-Seok Lee