Patents by Inventor Seung-Jin Yeom

Seung-Jin Yeom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER INCLUDING CRxBy AND METHOD FOR FORMING THE SAME
    Publication number: 20100059890
    Abstract: A metal line of a semiconductor device having a diffusion barrier including CrxBy and a method for forming the same is described. The metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer is formed having a metal line forming region. A diffusion barrier including a CrxBy layer is subsequently formed on the surface of the metal line forming region and the insulation layer. A metal line is finally formed to fill the metal line forming region of the insulation layer on the diffusion barrier including a CrxBy layer.
    Type: Application
    Filed: November 16, 2009
    Publication date: March 11, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Dong Ha JUNG, Seung Jin YEOM, Baek Mann KIM, Young Jin LEE, Jeong Tae KIM
  • METAL LINE HAVING A MOxSiy/Mo DIFFUSION BARRIER OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20100052167
    Abstract: A metal line having a MoxSiy/Mo diffusion barrier of a semiconductor device and corresponding methods of fabricating the same are presented. The metal line includes an insulation layer, a diffusion barrier, and a metal layer. The insulation layer is formed on a semiconductor substrate and has a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a stack structure composed of a MoxSiy layer and a Mo layer. The metal layer is formed on the diffusion barrier which fills in the metal line forming region of the insulation layer.
    Type: Application
    Filed: May 27, 2009
    Publication date: March 4, 2010
    Inventors: Joon Seok OH, Seung Jin YEOM, Baek Mann KIM, Dong Ha JUNG, Nam Yeal LEE, Jae Hong Kim
  • METAL LINE HAVING A MULTI-LAYERED DIFFUSION LAYER IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20100052168
    Abstract: A metal line having a multi-layered diffusion layer in a resultant semiconductor device is presented along with corresponding methods of forming the same. The metal line includes an insulation layer, a multi-layered diffusion barrier, and a metal layer. The insulation layer is formed on a semiconductor substrate and has a metal line forming region. The multi-layered diffusion barrier is formed on a surface of the metal line forming region defined in the insulation layer. The diffusion barrier includes a VB2 layer, a CrV layer and a Cr layer. The metal layer is formed on the diffusion barrier which substantially fills in the metal line forming region of the insulation layer to eventually form the metal line.
    Type: Application
    Filed: June 16, 2009
    Publication date: March 4, 2010
    Inventors: Dong Ha JUNG, Seung Jin YEOM, Baek Man KIM, Joon Seok OH, Nam Yeal LEE
  • METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME
    Publication number: 20100052170
    Abstract: A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer has a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier includes a multi-layered structure that includes an MoB2 layer, an MoxByNz layer and an Mo layer. A metal layer is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.
    Type: Application
    Filed: June 17, 2009
    Publication date: March 4, 2010
    Inventors: Dong Ha Jung, Seung Jin Yeom, Baek Mann Kim, Nam Yeal Lee
  • METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME
    Publication number: 20100052169
    Abstract: An insulation layer is formed on a semiconductor substrate so as to define a metal line forming region. A diffusion barrier having a multi-layered structure of an Mox1Si1-x1 layer, an Mox2Siy2Nz2 layer, and an Moy3N1-y3 layer is formed on a surface of the metal line forming region. A metal layer is formed on the diffusion barrier so as to fill the metal line forming region of the insulation layer.
    Type: Application
    Filed: June 17, 2009
    Publication date: March 4, 2010
    Inventors: Nam Yeal LEE, Seung Jin YEOM, Baek Mann KIM, Dong Ha JUNG, Joon Seok OH
  • Method for fabricating a cylindrical capacitor using amorphous carbon-based layer
    Patent number: 7670903
    Abstract: A method for fabricating a cylindrical capacitor. The method includes forming an isolation structure including an interlayer on a substrate, the substrate having a plurality of contact plugs formed therein, forming a plurality of opening regions by etching the isolation structure, thereby exposing selected portions of the contact plugs, forming storage nodes on a surface of the opening regions, etching selected portions of the isolation structure to form a patterned interlayer that encompasses selected portions of the storage nodes, thereby supporting the storage nodes, removing remaining portions of the isolation structure, and removing the patterned interlayer to expose inner and outer walls of the storage nodes.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: March 2, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Ki-Seon Park, Jae-Sung Roh, Deok-Sin Kil, Han-Sang Song, Seung-Jin Yeom, Jin-Hyock Kim, Kee-Jeung Lee
  • ELECTRICAL CONDUCTOR LINE HAVING A MULTILAYER DIFFUSION BARRIER FOR USE IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20100019386
    Abstract: An electrical conductor having a multilayer diffusion barrier of use in a resultant semiconductor device is presented. The electrical conductor line includes an insulation layer, a diffusion barrier, and a metal line. The insulation layer is formed on a semiconductor substrate and having a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a multi-layered structure made of TaN layer, an MoxOy layer and an Mo layer. The metal line is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.
    Type: Application
    Filed: May 21, 2009
    Publication date: January 28, 2010
    Inventors: Joon Seok OH, Seung Jin YEOM, Baek Man KIM, Dong Ha JUNG, Jeong Tae KIM, Nam Yeal LEE, Jae Hong KIM
  • CAPACITOR AND METHOD FOR FABRICATING THE SAME
    Publication number: 20100014212
    Abstract: A capacitor includes a lower electrode, a dielectric structure over the lower electrode, the dielectric structure including at least one crystallized zirconium oxide ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer, and an upper electrode formed over the dielectric structure. A method for fabricating a capacitor includes forming a lower electrode over a certain structure, forming a dielectric structure including at least one crystallized zirconium oxide (ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer over the lower electrode, and forming an upper electrode over the dielectric structure.
    Type: Application
    Filed: September 29, 2009
    Publication date: January 21, 2010
    Inventors: Deok-Sin Kil, Han-Sang Song, Seung-Jin Yeom, Ki-Seon Park, Jae-Sung Roh
  • Metal line of semiconductor device having a diffusion barrier including CRBand method for forming the same
    Patent number: 7638425
    Abstract: A metal line of a semiconductor device having a diffusion barrier including CrxBy and a method for forming the same is described. The metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer is formed having a metal line forming region. A diffusion barrier including a CrxBy layer is subsequently formed on the surface of the metal line forming region and the insulation layer. A metal line is finally formed to fill the metal line forming region of the insulation layer on the diffusion barrier including a CrxBy layer.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: December 29, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Ha Jung, Seung Jin Yeom, Baek Mann Kim, Young Jin Lee, Jeong Tae Kim
  • METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20090283908
    Abstract: A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate and a metal line forming region is formed in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer, and the diffusion layer has a multi-layered structure of an Ru layer, an RuxOy layer, an IrxOy layer, and a Ti layer. A metal layer is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.
    Type: Application
    Filed: December 8, 2008
    Publication date: November 19, 2009
    Inventors: Jeong Tae KIM, Seung Jin YEOM, Baek Mann KIM, Dong Ha JUNG, Joon Seok OH, Nam Yeal LEE, Jae Hong KIM
  • Capacitor and method for fabricating the same
    Patent number: 7616426
    Abstract: A capacitor includes a lower electrode, a dielectric structure over the lower electrode, the dielectric structure including at least one crystallized zirconium oxide (ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer, and an upper electrode formed over the dielectric structure. A method for fabricating a capacitor includes forming a lower electrode over a certain structure, forming a dielectric structure including at least one crystallized zirconium oxide (ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer over the lower electrode, and forming an upper electrode over the dielectric structure.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: November 10, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Deok-Sin Kil, Han-Sang Song, Seung-Jin Yeom, Ki-Seon Park, Jae-Sung Roh
  • METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE PREVENTING LOSS OF JUNCTION REGION
    Publication number: 20090269915
    Abstract: A method for manufacturing a semiconductor device includes forming an insulation layer having a contact hole on a semiconductor substrate. A metal silicide layer is deposited on a surface of the contact hole and the insulation layer to have a concentration gradient that changes from a silicon-rich composition to a metal-rich composition, with the lower portion of the metal silicide layer having the silicon-rich composition and the upper portion of the metal silicide layer having the metal-rich composition. The metal silicide layer is then annealed so that the compositions of metal and silicon in the metal silicide layer become uniform.
    Type: Application
    Filed: December 31, 2008
    Publication date: October 29, 2009
    Inventors: Dong Ha JUNG, Seung Jin YEOM, Baek Mann KIM, Chang Soo PARK, Jeong Tae KIM, Nam Yeal LEE
  • METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING DECREASED CONTACT RESISTANCE
    Publication number: 20090209096
    Abstract: A method for manufacturing a semiconductor device includes the steps of forming an insulation layer having a contact hole, on a semiconductor substrate, forming a Co layer on the insulation layer including a surface of the contact hole, conducting primary annealing to allow the Co layer and a portion of the semiconductor substrate to react with each other such that a CoSi layer is formed at an interface therebetween. The resultant semiconductor substrate is cleaned to remove a portion of the Co layer not having reacted in the primary annealing. A barrier layer is formed on the insulation layer, the CoSi layer, and the surface of the contact hole. A secondary annealing is conducted to convert the CoSi layer into a CoSi2 layer.
    Type: Application
    Filed: December 30, 2008
    Publication date: August 20, 2009
    Inventors: Nam Yeal LEE, Seung Jin YEOM, Baek Mann KIM, Dong Ha JUNG
  • METAL LINE OF SEMICONDUCTOR DEVICE WITHOUT PRODUCTION OF HIGH RESISTANCE COMPOUND DUE TO METAL DIFFUSION AND METHOD FOR FORMING THE SAME
    Publication number: 20090166871
    Abstract: A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and includes a WNx layer, a W—N—B ternary layer, and a Ti—N—B ternary layer. A wetting layer is formed on the diffusion barrier and is made of one of a Ti layer or a TiN layer. An upper metal line is formed on the wetting layer to fill the metal line forming region of the insulation layer.
    Type: Application
    Filed: December 5, 2008
    Publication date: July 2, 2009
    Inventors: Baek Mann KIM, Seung Jin YEOM, Dong Ha JUNG, Jeong Tae KIM
  • METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20090166870
    Abstract: A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate and having a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier has a multi-layered structure of a V layer, a VxNy layer and a VxNyOz layer. A metal layer is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.
    Type: Application
    Filed: December 2, 2008
    Publication date: July 2, 2009
    Inventors: Jeong Tae KIM, Seung Jin YEOM, Baek Mann KIM, Dong Ha JUNG
  • METHOD FOR FORMING THIN FILM
    Publication number: 20090148625
    Abstract: A method for forming a thin film by using an atomic layer deposition (ALD) method and a method for fabricating a capacitor using the same includes: supplying a source gas, a reaction gas, and a purge gas, then discontinuing the supply of the reaction gas and the source gas, followed by supplying and then discontinuing the supply of the reaction gas, wherein supplying the source gas, the reaction gas, and the purge gas, then discontinuing the supply of the reaction gas and the source gas, followed by supplying and then discontinuing the supply of the reaction gas constitutes a unit cycle, and repeating the unit cycle until a thin film having a desired thickness is deposited.
    Type: Application
    Filed: February 4, 2009
    Publication date: June 11, 2009
    Inventors: Seung-Jin Yeom, Deok-Sin Kil, Kwon Hong, Jae-Sung Roh
  • METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER WITH AN AMORPHOUS TaBN LAYER AND METHOD FOR FORMING THE SAME
    Publication number: 20090001578
    Abstract: A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A metal line is formed to fill the metal line forming region of the insulation layer. And a diffusion barrier that includes an amorphous TaBN layer is formed between the metal line and the insulation layer. The amorphous TaBN layer prevents a copper component from diffusing into the semiconductor substrate, thereby improving upon the characteristics and the reliability of a device.
    Type: Application
    Filed: November 14, 2007
    Publication date: January 1, 2009
    Inventors: Dong Ha JUNG, Seung Jin YEOM, Baek Mann KIM, Young Jin LEE, Jeong Tae KIM
  • METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20090004808
    Abstract: A method for fabricating a capacitor includes forming a sacrificial layer having a plurality of trenches on an upper portion of a substrate, forming storage nodes in the trenches, exposing upper portions of the storage nodes by removing a portion of the sacrificial layer, forming supporters to support the exposed upper portions of the storage nodes, removing the sacrificial layer under the supporters, and removing the supporters.
    Type: Application
    Filed: December 27, 2007
    Publication date: January 1, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kee-Jeung LEE, Jae-Sung Roh, Seung-Jin Yeom, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim, Kwan-Woo Do
  • METAL LINE OF SEMICONDUCTOR DEVICE WITH A TRIPLE LAYER DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME
    Publication number: 20090001577
    Abstract: A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region and a metal line is formed to fill the metal line forming region of the insulation layer. The diffusion barrier is formed between the metal line and the insulation layer. The diffusion barrier has a structure in which a TaSixNy layer is interposed between a first Ta-based layer and a second Ta-based layer. A metal line formed in this manner prevents the contact resistance of the metal line from increasing and the leakage current characteristics from degrading, thereby improving the device characteristics and reliability.
    Type: Application
    Filed: November 13, 2007
    Publication date: January 1, 2009
    Inventors: Jeong Tae KIM, Seung Jin YEOM, Baek Mann KIM, Young Jin LEE, Dong Ha JUNG
  • MULTI-LAYERED METAL LINE HAVING AN IMPROVED DIFFUSION BARRIER OF A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20090001579
    Abstract: A multi-layered metal line of a semiconductor device and a process of forming the same are described. The multi-layered metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is subsequently formed on the semiconductor substrate including the lower metal line and has an upper metal line forming region that exposes a portion of the lower metal line. A diffusion barrier formed on a surface of the upper metal line forming region of the insulation layer. The diffusion barrier includes a W—B—N ternary layer. An upper metal line is finally formed on the diffusion barrier to fill the upper metal line forming region of the insulation layer.
    Type: Application
    Filed: November 14, 2007
    Publication date: January 1, 2009
    Inventors: Baek Mann KIM, Seung Jin YEOM, Young Jin LEE, Dong Ha JUNG, Jeong Tae KIM