Abstract: The present invention is related to a ferroelectric memory device and a method for fabricating the same. The ferroelectric memory device includes: a substrate providing a transistor; a first insulation material with a plane surface formed on the substrate; a storage node contact passing through the first insulation material to contact to an active region of the substrate; a lower electrode being connected to the storage node contact and including a solid solution layer disposed at least as an upper most layer, the solid solution layer being doped with a metal element, which is induced to be in a solid solution state; a second insulation material having a plane surface that exposes a surface of the lower electrode, encompassing the lower electrode and being formed on the first insulation material; a ferroelectric layer covering the second insulation material including the lower electrode; an upper electrode formed on the ferroelectric layer.

Abstract: The present invention provides a ferroelectric memory device capable of suppressing a defect generation due to a charge impact and a method for fabricating the same. The ferroelectric memory device includes: a semiconductor substrate on which a transistor is formed; a semiconductor substrate structure having a transistor; a lower electrode formed on an interfacial insulation layer and connected to a source/drain region of the transistor; an isolating insulation layer on the interfacial insulation layer; a ferroelectric layer covering the isolating insulation layer and lower electrode; an oxygen vacancy compensation layer being formed on the ferroelectric layer and compensating an oxygen vacancy caused by deoxidization of a composition of the ferroelectric layer; and an upper electrode formed on the oxygen vacancy compensation layer.

Abstract: A semiconductor device, capable of precluding the deterioration of flatness and electrical properties due to the non-planarized topology and enhancing oxidative endurance and the process margins, which includes a conductive layer, an insulated layer formed on the conductive layer, a glue layer formed on the insulating layer, a connection unit, which is in contact with the conductive layer through the glue layer and the insulating layer and whose surface is planarized with that of the glue layer and a capacitor including a first electrode formed on the connection unit and the glue layer, a dielectric layer formed on the first electrode and a second electrode formed on the dielectric layer.

Abstract: The present invention provides a ferroelectric memory device capable of suppressing a defect generation due to a charge impact and a method for fabricating the same. The ferroelectric memory device includes: a semiconductor substrate on which a transistor is formed; a semiconductor substrate structure having a transistor; a lower electrode formed on an interfacial insulation layer and connected to a source/drain region of the transistor; an isolating insulation layer on the interfacial insulation layer; a ferroelectric layer covering the isolating insulation layer and lower electrode; an oxygen vacancy compensation layer being formed on the ferroelectric layer and compensating an oxygen vacancy caused by deoxidization of a composition of the ferroelectric layer; and an upper electrode formed on the oxygen vacancy compensation layer.

Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory device. The method includes the steps of: (a) forming a first inter-layer insulation layer on a substrate providing a transistor; (b) etching the first inter-layer insulation layer to form a storage node contact hole exposing a partial portion of the substrate; (c) burying a storage node contact including a plug and a barrier metal layer into the storage node contact hole; (d) forming an adhesion layer on the storage node contact and the first inter-layer insulation layer; (e) inducing a predetermined portion of the adhesion layer to be cracked, the predetermined portion disposed above an upper part of the plug; (f) selectively removing the cracked predetermined portion to expose a surface of the barrier metal layer formed on the plug; and (g) forming a ferroelectric capacitor connected to the plug through the exposed surface of the barrier metal layer.

Abstract: The present invention provides a ferroelectric memory device capable of suppressing a defect generation due to a charge impact and a method for fabricating the same. The ferroelectric memory device includes: a semiconductor substrate on which a transistor is formed; a semiconductor substrate structure having a transistor; a lower electrode formed on an interfacial insulation layer and connected to a source/drain region of the transistor; an isolating insulation layer on the interfacial insulation layer; a ferroelectric layer covering the isolating insulation layer and lower electrode; an oxygen vacancy compensation layer being formed on the ferroelectric layer and compensating an oxygen vacancy caused by deoxidization of a composition of the ferroelectric layer; and an upper electrode formed on the oxygen vacancy compensation layer.

Abstract: The inventive ferroelectric memory device includes: a semiconductor substrate providing elements of a transistor; a first inter-layer insulating layer formed on the semiconductor substrate; a storage node contact connected to elements of the transistor by passing through the first inter-layer insulating layer; a barrier layer contacting simultaneously to the storage node contact and the first inter-layer insulating layer; a lower electrode having a space for isolating the first inter-layer insulating layer and being formed on the barrier layer; a glue layer being formed on the first inter-layer insulating layer and encompassing lateral sides of the lower electrode as filling the space; a second inter-layer insulating layer exposing a surface of the lower electrode and encompassing the glue layer; a ferroelectric layer formed on the glue layer including the second inter-layer insulating layer; and an upper electrode formed on the ferroelectric layer.

Abstract: A ferroelectric memory device and a method for manufacturing the same is disclosed. Because a (BixLay)Ti3O12 (BLT) layer, which can be crystallized in relatively low temperature, is used in a capacitor, the electrical characteristics of the ferroelectric capacitor can be improved. The method for manufacturing ferroelectric memory device includes the steps of forming a first conductive layer for a bottom electrode on a semiconductor substrate, forming the (BixLay)Ti3O12 ferroelectric layer, wherein ‘x’ representing atomic concentration of Bi ranges from about 3.25 to about 3.35 and ‘y’ representing atomic concentration of La ranges from about 0.70 to about 0.90 and forming a second conductive layer for a top electrode on the (BixLay)Ti3O12 ferroelectric layer.

Abstract: The present invention is related to a ferroelectric memory device and a method for fabricating the same. The ferroelectric memory device includes: a substrate providing a transistor; a first insulation material with a plane surface formed on the substrate; a storage node contact passing through the first insulation material to contact to an active region of the substrate; a lower electrode being connected to the storage node contact and including a solid solution layer disposed at least as an upper most layer, the solid solution layer being doped with a metal element, which is induced to be in a solid solution state; a second insulation material having a plane surface that exposes a surface of the lower electrode, encompassing the lower electrode and being formed on the first insulation material; a ferroelectric layer covering the second insulation material including the lower electrode; an upper electrode formed on the ferroelectric layer.

Abstract: A semiconductor device for use in a memory cell includes an active matrix provided with a silicon substrate, a transistor formed on the silicon substrate, a capacitor structure formed over the transistor, a metal interconnection for electrically connecting the capacitor structure to the transistor, a barrier layer formed on top of the metal interconnection and an inter-metal dielectric (IMD) layer formed on top of the barrier layer, wherein the barrier layer is made of a material such as A12O3 or the like. The IMD layer is formed by using a plasma chemical vapor deposition (CVD) in a hydrogen rich atmosphere, wherein the barrier layer is used for preventing the capacitor structure from the hydrogen.

Abstract: A semiconductor memory device is provided which prevents a lifting phenomenon by improving an adhesive strength between an upper electrode and an interlayer insulating layer. The semiconductor memory device includes a capacitor formed on a semiconductor substrate, wherein the capacitor includes a lower electrode, a dielectric layer and an upper electrode; an adhesion layer formed on the upper -electrode; an interlayer insulating layer covering the capacitor, wherein a portion of the interlayer insulating layer is in contact with the adhesion layer; and a contact hole, formed within the interlayer insulating layer, whose bottom exposes the upper electrode and whose sidewalls expose the interlayer insulating layer and the adhesion layer.

Abstract: A semiconductor device, capable of precluding the deterioration of flatness and electrical properties due to the non-planarized topology and enhancing oxidative endurance and the process margins, which includes a conductive layer, an insulated layer formed on the conductive layer, a glue layer formed on the insulating layer, a connection unit, which is in contact with the conductive layer through the glue layer and the insulating layer and whose surface is planarized with that of the glue layer and a capacitor including a first electrode formed on the connection unit and the glue layer, a dielectric layer formed on the first electrode and a second electrode formed on the dielectric layer.

Abstract: A semiconductor device includes a first insulating layer formed on a semiconductor substrate including a conductive layer. A plug passes through the first insulating layer and connects to the conductive layer in the semiconductor substrate. A barrier layer is formed on the plug. A second insulating layer is formed, through a planarization process, to be an equal height to that of the barrier layer on the first insulating layer. A capacitor is formed on the barrier layer.

Abstract: A semiconductor memory device is provided which prevents a lifting phenomenon by improving an adhesive strength between an upper electrode and an interlayer insulating layer. The semiconductor memory device includes a capacitor formed on a semiconductor substrate, wherein the capacitor includes a lower electrode, a dielectric layer and an upper electrode; an adhesion layer formed on the upper electrode; an interlayer insulating layer covering the capacitor, wherein a portion of the interlayer insulating layer is in contact with the adhesion layer; and a contact hole, formed within the interlayer insulating layer, whose bottom exposes the upper electrode and whose sidewalls expose the interlayer insulating layer and the adhesion layer.

Abstract: A ferroelectric memory device and a method for manufacturing the same is disclosed. Because a (BixLay)Ti3O12 (BLT) layer, which can be crystallized in relatively low temperature, is used in a capacitor, the electrical characteristics of the ferroelectric capacitor can be improved. The method for manufacturing ferroelectric memory device includes the steps of forming a first conductive layer for a bottom electrode on a semiconductor substrate, forming the (BixLay)Ti3O12 ferroelectric layer, wherein ‘x’ representing atomic concentration of Bi ranges from about 3.25 to about 3.35 and ‘y’ representing atomic concentration of La ranges from about 0.70 to about 0.90 and forming a second conductive layer for a top electrode on the (BixLay)Ti3O12 ferroelectric layer.

Abstract: A method for fabricating a capacitor in a semiconductor device includes forming a semiconductor device having a source, a drain, and a gate on a semiconductor substrate, forming an interlayer insulating film having a contact hole exposing the source, forming a conductive layer in the contact hole, forming a lower electrode on the interlayer insulating film, inclusive of the conductive layer, coating an insulating material on the lower electrode for forming a dielectric film, subjecting the insulating material to a first rapid thermal annealing of a first temperature in a chamber, to form nuclei oriented along an a-b axis, subjecting the insulating material to a second rapid thermal annealing at a second temperature higher than the first temperature in the chamber, to grow the nuclei oriented along the a-b axis, to form a dielectric film, and forming an upper electrode on the dielectric film.

Abstract: A semiconductor fabrication technique for forming a ferroelectric capacitor, in which the thermal burden is reduced by using an SBT-based ferroelectric thin film such as SrxBiyTa2O9 (‘SBT’) or SrxBiy(TaiNbj)2O9 (‘SBT(N)’) as the dielectric medium. The method includes the following steps. A strontium-bismuth-tantalum oxide film is formed on a semiconductor substrate, with a conductive film for a lower electrode having been formed on the semiconductor substrate (first step). An NH3 gas is flowed at a stabilizing step of a rapid thermal annealing so as to reduce organic materials bonded with metal elements of the strontium-bismuth-tantalum oxide film (second step). An oxide gas is flowed at a temperature of 450˜650° C. at an annealing step of the rapid thermal annealing so as to induce a perovskite nuclear formation in the strontium-bismuth-tantalum oxide film (third step).

Abstract: A method for manufacturing a semiconductor device comprises the steps of providing a semiconductor substrate, forming an interlayer insulating layer on the semiconductor substrate, forming a contact hole in the interlayer insulating layer, forming a plug recessed inside of the contact hole, forming an ohmic contact layer on the plug, depositing a La layer or a LaN layer on the ohmic contact layer, performing a nitridation process by a plasma treatment process to form a LaN diffusion barrier layer on the ohmic contact layer and sequentially forming a bottom electrode, a BLT ((BixLay)Ti3O12) dielectric layer and a top electrode on the entire structure.

Abstract: A method for fabricating a capacitor in a semiconductor device includes forming a semiconductor device having a source, a drain, and a gate on a semiconductor substrate, forming an interlayer insulating film having a contact hole exposing the source, forming a conductive layer in the contact hole, forming a lower electrode on the interlayer insulating film, inclusive of the conductive layer, coating an insulating material on the lower electrode for forming a dielectric film, subjecting the insulating material to a first rapid thermal annealing of a first temperature in a chamber, to form nuclei oriented along an a-b axis, subjecting the insulating material to a second rapid thermal annealing at a second temperature higher than the first temperature in the chamber, to grow the nuclei oriented along the a-b axis, to form a dielectric film, and forming an upper electrode on the dielectric film.

Abstract: A semiconductor fabrication technique for forming a ferroelectric capacitor, in which the thermal burden is reduced by using an SBT-based ferroelectric thin film such as SrxBiyTa2O9 (‘SBT’) or SrxBiy(TaiNbj)2O9 (‘SBT(N)’) as the dielectric medium. The method includes the following steps. A strontium-bismuth-tantalum oxide film is formed on a semiconductor substrate, with a conductive film for a lower electrode having been formed on the semiconductor substrate (first step). An NH3 gas is flowed at a stabilizing step of a rapid thermal annealing so as to reduce organic materials bonded with metal elements of the strontium-bismuth-tantalum oxide film (second step). An oxide gas is flowed at a temperature of 450˜650° C. at an annealing step of the rapid thermal annealing so as to induce a perovskite nuclear formation in the strontium-bismuth-tantalum oxide film (third step).