Abstract: An inverter module according to an embodiment of the present invention comprises: a high voltage circuit unit which generates an inverter control voltage and a motor driving voltage by using a first DC voltage; a high voltage circuit pattern which electrically connects the high voltage circuit unit; a low voltage circuit unit which communicates with an external device by using a second DC voltage having a smaller magnitude than the first DC voltage; and a low voltage circuit pattern which electrically connects the low voltage circuit unit. The high voltage circuit pattern and the low voltage circuit pattern are spaced apart from each other.

Abstract: The present disclosure relates to an organic electroluminescent compound, a plurality of host materials, and an organic electroluminescent device comprising the same. By comprising the compound according to the present disclosure or by comprising a specific combination of compounds according to the present disclosure as a plurality of host materials, it is possible to produce an organic electroluminescent device having improved driving voltage, luminous efficiency, and/or lifetime properties compared to the conventional organic electroluminescent devices.

Abstract: The present invention relates to a twisted string actuator. The present invention may comprise: a drive source; driving parts for receiving power from the driving source; driven parts installed in conjunction with the driving parts and receiving power; strings coupled to the ends of the driving parts and the driven parts so as to be twisted or untwisted, and a driving compensation part installed at the ends of the strings to compensate for uneven actuation of each of the strings.

Abstract: Provided is a peptide composition for preventing or treating Alzheimer's dementia. A peptide or a salt substituent thereof according to the presently claimed subject matter exhibits effects such as suppression of LPS-mediated cytokine production, suppression of LPS-induced neuroinflammation, amelioration of cognitive impairment, suppression of beta amyloid or tau protein aggregation, and suppression of neuronal loss. The polypeptide or the salt substituent thereof can permeate the blood-brain barrier, and thus, is expected to be usefully used for preventing or treating Alzheimer's dementia.

Abstract: There is provided a method for providing driver's driving information of a user terminal device, including accessing a driving information providing server storing data generated in a driving recording device for a vehicle, receiving driving record data including event record data corresponding to a driving-related event of a driver from the driving information providing server, and displaying a driving-related event occurrence location on a map using the received driving record data. The driving-related event may include at least two or more of a lane departure event, a forward collision possibility event, a rear side collision possibility event, a sudden deceleration event, a sudden acceleration event, a sudden stop event, a sudden start event, and a speeding event.

Abstract: An apparatus of tilting a seat cushion of a vehicle, includes a tilting motor, a pinion gear, a sector gear, and a tilting link which perform the tilting operation of the seat cushion and exert a binding force in a tilted state of the seat cushion and are provided to be connected to both of one side and the other side of a seat cushion frame, and has two sector gears positioned on left and right sides and connected to each other by a connection bar so that, by strengthening a binding force of the front portion of the seat cushion, it is possible to secure the safety of passengers in the event of a collision.

Abstract: A memory system, including a memory controller and a memory, wherein the memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller mixes a second command with the first command and transmits the mixture of the first command and the second command. The memory changes command latch timing depends on the first or second mode.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

Abstract: An apparatus for controlling a transmission of a vehicle includes a processor configured to identify a location of a speed bump based on collected information about a specified section of a front road and determine whether the vehicle enters a section of the speed bump, and to set an oil pressure of the transmission to a first oil pressure in a normal driving section and set the oil pressure of the transmission to a second oil pressure when the vehicle enters the section of the speed bump, and a controller that controls the oil pressure of the transmission corresponding to a setting of the processor for each driving section of the vehicle.

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.