Patents by Inventor Seung Jun Shin
Seung Jun Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11081152Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.Type: GrantFiled: May 15, 2020Date of Patent: August 3, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jun Shin, Tae-Young Oh
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Patent number: 10950704Abstract: A vertical memory device includes a substrate including a cell array region and a staircase region surrounding the cell array region, gate electrodes on the cell array region and the staircase region, and a channel on the cell array region. The gate electrodes are isolated from each other in first and third directions and each extend in a second direction. The channel extends in the first direction through one or more gate electrodes. End portions in the second direction of first gate electrodes of the plurality of gate electrodes define first steps in the second direction and second steps in the third direction on the staircase region of the substrate, the second steps being connected to the first steps, respectively, at same levels.Type: GrantFiled: June 14, 2019Date of Patent: March 16, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jun Shin, Si-Wan Kim, Bong-Hyun Choi
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Patent number: 10930671Abstract: A vertical memory device includes a substrate having a cell array region and a staircase region. Gate electrodes are spaced apart from each other in first and third directions. A channel extends through the gate electrodes in the first direction on the cell array region. Each of the gate electrodes extends in a second direction. End portions in the second direction of one or more of the gate electrodes form a first stair structure on the staircase region of the substrate. The first stair structure includes first steps, a second step, and a third step sequentially disposed in the third direction. Each of the first steps has a first length, the second step has a second length greater than the first length, and the third step has a third length greater than the second length.Type: GrantFiled: July 17, 2019Date of Patent: February 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Jun Shin, Bong-Hyun Choi
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Patent number: 10930330Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.Type: GrantFiled: December 17, 2019Date of Patent: February 23, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jun Shin, Tae-Young Oh
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Publication number: 20200356290Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeon-kyu CHOI, Ki-seok OH, Seung-jun SHIN, Hye-ran KIM
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Publication number: 20200303413Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.Type: ApplicationFiled: June 4, 2020Publication date: September 24, 2020Inventors: Seung Jun SHIN, Hyun Mog PARK, Joong Shik SHIN
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Publication number: 20200278790Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.Type: ApplicationFiled: May 15, 2020Publication date: September 3, 2020Inventors: Seung-Jun SHIN, Tae-Young OH
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Patent number: 10754564Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.Type: GrantFiled: October 30, 2017Date of Patent: August 25, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeon-kyu Choi, Ki-seok Oh, Seung-jun Shin, Hye-ran Kim
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Publication number: 20200256464Abstract: An apparatus for controlling a transmission of a vehicle includes a processor configured to identify a location of a speed bump based on collected information about a specified section of a front road and determine whether the vehicle enters a section of the speed bump, and to set an oil pressure of the transmission to a first oil pressure in a normal driving section and set the oil pressure of the transmission to a second oil pressure when the vehicle enters the section of the speed bump, and a controller that controls the oil pressure of the transmission corresponding to a setting of the processor for each driving section of the vehicle.Type: ApplicationFiled: August 29, 2019Publication date: August 13, 2020Inventors: Kwang Hee Park, Sang Jun Park, Seung Jun Shin, Byeong Wook Jeon, Jae Chang Kook
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Publication number: 20200203495Abstract: A vertical memory device includes a substrate including a cell array region and a staircase region surrounding the cell array region, gate electrodes on the cell array region and the staircase region, and a channel on the cell array region. The gate electrodes are isolated from each other in first and third directions and each extend in a second direction. The channel extends in the first direction through one or more gate electrodes. End portions in the second direction of first gate electrodes of the plurality of gate electrodes define first steps in the second direction and second steps in the third direction on the staircase region of the substrate, the second steps being connected to the first steps, respectively, at same levels.Type: ApplicationFiled: June 14, 2019Publication date: June 25, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Seung-Jun SHIN, Si-Wan Kim, Bong-Hyun Choi
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Patent number: 10680007Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.Type: GrantFiled: March 23, 2018Date of Patent: June 9, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Jun Shin, Hyun Mog Park, Joong Shik Shin
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Patent number: 10671319Abstract: A memory device includes first and second bank groups, an internal command generator, and an address input/output circuit. Each of the bank groups includes a plurality of banks. The internal command generator generates and outputs internal commands to a first target bank. The internal commands are generated based on a command from a memory controller for controlling a memory operation of the first target bank. The address input/output (I/O) circuit receive a first address corresponding to the command, selects a storage path of the first address based on whether there is a bubble interval in a data burst operation interval corresponding to the first command, controls output of the first address in accordance with a time point at which each of the internal commands is output. The first address is stored in the address I/O circuit.Type: GrantFiled: June 18, 2018Date of Patent: June 2, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-jun Shin, Hyong-ryol Hwang
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Publication number: 20200125257Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.Type: ApplicationFiled: December 17, 2019Publication date: April 23, 2020Inventors: Seung-Jun SHIN, Tae-Young OH
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Publication number: 20200119043Abstract: A vertical memory device includes a substrate having a cell array region and a staircase region. Gate electrodes are spaced apart from each other in first and third directions. A channel extends through the gate electrodes in the first direction on the cell array region. Each of the gate electrodes extends in a second direction. End portions in the second direction of one or more of the gate electrodes form a first stair structure on the staircase region of the substrate. The first stair structure includes first steps, a second step, and a third step sequentially disposed in the third direction. Each of the first steps has a first length, the second step has a second length greater than the first length, and the third step has a third length greater than the second length.Type: ApplicationFiled: July 17, 2019Publication date: April 16, 2020Inventors: SEUNG-JUN SHIN, BONG-HYUN CHOI
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Patent number: 10579263Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.Type: GrantFiled: October 24, 2018Date of Patent: March 3, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Jun Shin, Tae-Young Oh
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Patent number: 10497422Abstract: A memory device includes a memory cell array, a refresh controller, and control logic. The memory cell array includes a plurality of rows. The refresh controller performs a refresh operation on the plurality of rows. The control logic controls a care operation on a first adjacent region that is most adjacent to a first row based on a number of times the plurality of rows are accessed during a first period. The control logic also controls a care operation on a second adjacent region that is second adjacent to a second row based on a number of times the plurality of rows are accessed during a second period. The first and second periods are different periods.Type: GrantFiled: January 12, 2018Date of Patent: December 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-jun Lee, Seung-jun Shin, Hoon Sin, Ik-joon Choi, Ju-seong Hwang
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Publication number: 20190138245Abstract: A memory device includes first and second bank groups, an internal command generator, and an address input/output circuit. Each of the bank groups includes a plurality of banks. The internal command generator generates and outputs internal commands to a first target bank. The internal commands are generated based on a command from a memory controller for controlling a memory operation of the first target bank. The address input/output (I/O) circuit receive a first address corresponding to the command, selects a storage path of the first address based on whether there is a bubble interval in a data burst operation interval corresponding to the first command, controls output of the first address in accordance with a time point at which each of the internal commands is output. The first address is stored in the address I/O circuit.Type: ApplicationFiled: June 18, 2018Publication date: May 9, 2019Inventors: Seung-jun SHIN, Hyong-ryol HWANG
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Publication number: 20190065050Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.Type: ApplicationFiled: October 24, 2018Publication date: February 28, 2019Inventors: Seung-Jun SHIN, Tae-Young OH
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Publication number: 20190027490Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.Type: ApplicationFiled: March 23, 2018Publication date: January 24, 2019Inventors: Seung Jun SHIN, Hyun Mog PARK, Joong Shik SHIN
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Publication number: 20180342283Abstract: A memory device includes a memory cell array, a refresh controller, and control logic. The memory cell array includes a plurality of rows. The refresh controller performs a refresh operation on the plurality of rows. The control logic controls a care operation on a first adjacent region that is most adjacent to a first row based on a number of times the plurality of rows are accessed during a first period. The control logic also controls a care operation on a second adjacent region that is second adjacent to a second row based on a number of times the plurality of rows are accessed during a second period. The first and second periods are different periods.Type: ApplicationFiled: January 12, 2018Publication date: November 29, 2018Inventors: Seung-jun LEE, Seung-jun SHIN, Hoon SIN, Ik-joon CHOI, Ju-seong HWANG