Patents by Inventor Seung-Kon Mok
Seung-Kon Mok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230215824Abstract: A semiconductor package having a thinner shape and including an antenna is provided. A semiconductor package comprises a first substrate, a second substrate on the first substrate and including a first face facing the first substrate and a second face opposite to the first face, a pillar extending from the second face of the second substrate to the first substrate, and a first semiconductor chip on the second face of the second substrate and connected to the pillar. The second substrate may include an antenna pattern, and the antenna pattern may be connected to the first semiconductor chip, and may be on the second face of the second substrate such that the antenna pattern is isolated from direct contact with the first semiconductor chip.Type: ApplicationFiled: March 10, 2023Publication date: July 6, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Se Ho YOU, Hyeong Seob Kim, Seung Kon Mok
-
Patent number: 11626373Abstract: A semiconductor package having a thinner shape and including an antenna is provided. A semiconductor package comprises a first substrate, a second substrate on the first substrate and including a first face facing the first substrate and a second face opposite to the first face, a pillar extending from the second face of the second substrate to the first substrate, and a first semiconductor chip on the second face of the second substrate and connected to the pillar. The second substrate may include an antenna pattern, and the antenna pattern may be connected to the first semiconductor chip, and may be on the second face of the second substrate such that the antenna pattern is isolated from direct contact with the first semiconductor chip.Type: GrantFiled: February 10, 2021Date of Patent: April 11, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Se Ho You, Hyeong Seob Kim, Seung Kon Mok
-
Publication number: 20210398924Abstract: A semiconductor package having a thinner shape and including an antenna is provided. A semiconductor package comprises a first substrate, a second substrate on the first substrate and including a first face facing the first substrate and a second face opposite to the first face, a pillar extending from the second face of the second substrate to the first substrate, and a first semiconductor chip on the second face of the second substrate and connected to the pillar. The second substrate may include an antenna pattern, and the antenna pattern may be connected to the first semiconductor chip, and may be on the second face of the second substrate such that the antenna pattern is isolated from direct contact with the first semiconductor chip.Type: ApplicationFiled: February 10, 2021Publication date: December 23, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Se Ho YOU, Hyeong Seob KIM, Seung Kon MOK
-
Patent number: 10483150Abstract: An apparatus for stacking semiconductor chips includes a push member configured to apply pressure to a semiconductor chip disposed on a substrate. The push member includes a push plate configured to contact the semiconductor chip, and a push rod connected to the push plate. The push plate includes a central portion having an area smaller than an area of an upper side of the semiconductor chip, and a plurality of protrusions disposed at respective ends of the central portion.Type: GrantFiled: November 11, 2016Date of Patent: November 19, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Gun-Ah Lee, Ji-Hwan Hwang, Cha-Jea Jo, Dong-Han Kim, Seung-Kon Mok
-
Patent number: 9793309Abstract: Provided is an image sensor package that includes a transparent protection cover for protecting a plurality of unit pixels each including a microlens. The image sensor package includes a substrate which has a first surface and a second surface that are opposite to each other, and includes a sensor array region including a plurality of unit pixels formed in the first surface and a pad region including a pad arranged in the vicinity of the sensor array region, a plurality of microlenses formed on the plurality of unit pixels, respectively, at least two transparent material layers covering the plurality of microlenses, and a transparent protection cover attached onto the plurality of microlenses with the at least two transparent material layers interposed therebetween.Type: GrantFiled: January 26, 2015Date of Patent: October 17, 2017Assignees: SAMSUNG ELECTRONICS CO., LTD., FUREX CO., LTD.Inventors: Byoung-rim Seo, Yoon-young Choi, Kyoung-sei Choi, Chang-soo Jin, Seung-kon Mok, Tae-weon Suh, Pyoung-wan Kim
-
Publication number: 20170236798Abstract: An apparatus for stacking semiconductor chips includes a push member configured to apply pressure to a semiconductor chip disposed on a substrate. The push member includes a push plate configured to contact the semiconductor chip, and a push rod connected to the push plate. The push plate includes a central portion having an area smaller than an area of an upper side of the semiconductor chip, and a plurality of protrusions disposed at respective ends of the central portion.Type: ApplicationFiled: November 11, 2016Publication date: August 17, 2017Inventors: GUN-AH LEE, Jl-HWAN HWANG, CHA-JEA JO, DONG-HAN KIM, SEUNG-KON MOK
-
Publication number: 20150340397Abstract: Provided is an image sensor package that includes a transparent protection cover for protecting a plurality of unit pixels each including a microlens. The image sensor package includes a substrate which has a first surface and a second surface that are opposite to each other, and includes a sensor array region including a plurality of unit pixels formed in the first surface and a pad region including a pad arranged in the vicinity of the sensor array region, a plurality of microlenses formed on the plurality of unit pixels, respectively, at least two transparent material layers covering the plurality of microlenses, and a transparent protection cover attached onto the plurality of microlenses with the at least two transparent material layers interposed therebetween.Type: ApplicationFiled: January 26, 2015Publication date: November 26, 2015Applicant: FUREX CO., LTD.Inventors: Byoung-rim SEO, Yoon-young CHOI, Kyoung-sei CHOI, Chang-soo JIN, Seung-kon MOK, Tae-weon SUH, Pyoung-wan KIM
-
Patent number: 9190401Abstract: Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.Type: GrantFiled: May 23, 2014Date of Patent: November 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Choong-Bin Yim, Seung-Kon Mok, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim
-
Publication number: 20140256089Abstract: Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Choong-Bin YIM, Seung-Kon MOK, Jin-Woo PARK, Dae-Young CHOI, Mi-Yeon KIM
-
Patent number: 8803301Abstract: A semiconductor package may include a substrate, a semiconductor chip disposed on the substrate, a communication terminal and a static electricity inducing terminal connected to a ground. The package may include a first sealant that comprises a voltage sensitive material and that covers the semiconductor chip and a static electricity blocking layer that provides a conductive pathway from the first sealant to only the static electric inducing terminal. The static electricity blocking layer may prevent the communication terminal from being electrically connected to the first sealant. If a buildup of charge is applied to the device, the first sealant may become polarized and/or conductive. The extra voltage may travel through the first sealant to the static electricity inducing terminal via an opening in the static electricity blocking layer. The semiconductor chip and the communication terminal may not be affected by the extra charge.Type: GrantFiled: March 22, 2012Date of Patent: August 12, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kyong-soon Cho, Seung-kon Mok, Kwan-jai Lee, Jae-min Jung
-
Patent number: 8759959Abstract: Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.Type: GrantFiled: February 17, 2011Date of Patent: June 24, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Choong-Bin Yim, Seung-Kon Mok, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim
-
Publication number: 20120274868Abstract: A semiconductor package may include a substrate, a semiconductor chip disposed on the substrate, a communication terminal and a static electricity inducing terminal connected to a ground. The package may include a first sealant that comprises a voltage sensitive material and that covers the semiconductor chip and a static electricity blocking layer that provides a conductive pathway from the first sealant to only the static electric inducing terminal. The static electricity blocking layer may prevent the communication terminal from being electrically connected to the first sealant. If a buildup of charge is applied to the device, the first sealant may become polarized and/or conductive. The extra voltage may travel through the first sealant to the static electricity inducing terminal via an opening in the static electricity blocking layer. The semiconductor chip and the communication terminal may not be affected by the extra charge.Type: ApplicationFiled: March 22, 2012Publication date: November 1, 2012Inventors: Kyong-soon Cho, Seung-kon Mok, Kwan-jai Lee, Jae-min Jung
-
Publication number: 20110215451Abstract: Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.Type: ApplicationFiled: February 17, 2011Publication date: September 8, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Choong-Bin Yim, Seung-Kon Mok, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim
-
Patent number: 7952199Abstract: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the center portion of the base substrate and the land hole disposed at the edge portion of the base substrate may have different sizes. For example, the sizes of the land holes may increase from the center portion of the base substrate to the edge portion thereof, and alternatively, the sizes of the land holes may decrease from the center portion of the base substrate to the edge portion thereof.Type: GrantFiled: January 8, 2010Date of Patent: May 31, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Gui Jo, Seung-Kon Mok, Han-Shin Youn
-
Publication number: 20100116539Abstract: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the center portion of the base substrate and the land hole disposed at the edge portion of the base substrate may have different sizes. For example, the sizes of the land holes may increase from the center portion of the base substrate to the edge portion thereof, and alternatively, the sizes of the land holes may decrease from the center portion of the base substrate to the edge portion thereof.Type: ApplicationFiled: January 8, 2010Publication date: May 13, 2010Inventors: Sang-Gui Jo, Seung-Kon Mok, Han-Shin Youn
-
Patent number: 7667325Abstract: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the center portion of the base substrate and the land hole disposed at the edge portion of the base substrate may have different sizes. For example, the sizes of the land holes may increase from the center portion of the base substrate to the edge portion thereof, and alternatively, the sizes of the land holes may decrease from the center portion of the base substrate to the edge portion thereof.Type: GrantFiled: May 7, 2007Date of Patent: February 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Gui Jo, Seung-Kon Mok, Han-Shin Youn
-
Publication number: 20090315130Abstract: A solid-state imaging apparatus and method for manufacturing the imaging apparatus. A solid-state imaging apparatus with reduced thickness and/or mounting area by forming an aperture in a board and placing a solid-state semiconductor imaging chip, an image processing semiconductor chip, and/or a combination imaging/processing chip within the aperture.Type: ApplicationFiled: August 11, 2004Publication date: December 24, 2009Inventors: Young-Hoon Ro, Young-Shin Kwon, Seung-Kon Mok
-
Patent number: 7579583Abstract: A size reduced solid-state imaging apparatus may be provided. The solid-state imaging apparatus may include a wiring substrate having a body having a cavity on an area which a semiconductor chip may be mounted, a lead that may project inward into the cavity from the internal side of the body, and/or a tie bar.Type: GrantFiled: November 1, 2004Date of Patent: August 25, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Kon Mok, Young-Hoon Ro
-
Publication number: 20090108447Abstract: A semiconductor device is provided, including a semiconductor chip having fine pitch bond pads, dummy bond pads, and ball bonds formed on the semiconductor chip, and electrically connected to circuits of the semiconductor chip, where the width of each fine pitch bond pad is less than the diameter of each ball bond. The dummy bond pads are formed between adjacent bond pads and have a plurality of lands not connected to each other. The ball bonds may be connected to the bond pads in a zigzag configuration and are partially connected to the dummy bond pads. Accordingly, the pitch between bond pads is reduced while preventing short circuits between adjacent ball bonds.Type: ApplicationFiled: October 1, 2008Publication date: April 30, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Gui JO, Seung-Kon MOK
-
Publication number: 20090057845Abstract: An apparatus to saw a wafer and having a nozzle to remove burrs in scribe lanes, a method of sawing a wafer, and a semiconductor package fabricated by the same. The apparatus includes a blade to cut scribe lanes of the wafer and a burr removing nozzle disposed spaced apart from the blade. The burr removing nozzle removes metal burrs generated adjacent to the blade during cutting the wafer.Type: ApplicationFiled: September 4, 2008Publication date: March 5, 2009Applicant: Samsung Electronics Co., LtdInventors: Ji-Sun Hong, Seung-Kon Mok, Tae-Hun Kim