Patents by Inventor Seung-Man Shin
Seung-Man Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136620Abstract: Discussed is a battery pack that may include at least one battery module including at least one battery cell; a case tray configured to support the at least one battery module; a tray cover coupled to the case tray; and at least one bushing gasket configured to connect the case tray and the tray cover and to support the case tray on a plurality of points.Type: ApplicationFiled: October 6, 2022Publication date: April 25, 2024Applicant: LG ENERGY SOLUTION, LTD.Inventors: Young-Jin KIM, Yong-Shik SHIN, Do-Wung SON, Seung-Hyun YUN, Byeong-Yoon JUNG, Sung-Man CHOI
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Patent number: 9298612Abstract: A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.Type: GrantFiled: August 30, 2013Date of Patent: March 29, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Sung Shin, Sang-Joon Hwang, Seung-Man Shin, In-Su Choi, Jung-Ho Jung
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Patent number: 8976615Abstract: A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The semiconductor memory device is configured such that when a read command or a write command is input, if a first portion of a plurality of memory banks of a first memory bank group from among one or more memory bank groups of the memory cell array performs a read operation or a write operation, a second portion of the plurality of memory banks of the first memory bank group performs a refresh operation.Type: GrantFiled: August 20, 2013Date of Patent: March 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Sung Shin, Seung-Man Shin, In-Su Choi
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Publication number: 20140143478Abstract: A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.Type: ApplicationFiled: August 30, 2013Publication date: May 22, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Hyun-Sung SHIN, Sang-Joon HWANG, Seung-Man SHIN, In-Su CHOI, Jung-Ho JUNG
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Publication number: 20140078846Abstract: A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The semiconductor memory device is configured such that when a read command or a write command is input, if a first portion of a plurality of memory banks of a first memory bank group from among one or more memory bank groups of the memory cell array performs a read operation or a write operation, a second portion of the plurality of memory banks of the first memory bank group performs a refresh operation.Type: ApplicationFiled: August 20, 2013Publication date: March 20, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Sung SHIN, Seung-Man SHIN, In-Su CHOI
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Patent number: 8298092Abstract: A tripod type constant velocity joint comprises a housing having three track grooves defined at trisected positions of the housing and extending in an axial direction, and a spider having three -trunnions projectedly formed at trisected positions of the spider to be respectively inserted into the track grooves, each trunnion having a generally oval or elliptical cross-sectional shape and including at least one independent contact surface at each of two opposing sides subjecting to a load. Inner rollers each has an inner surface of a concavely curved contour for receiving a corresponding trunnion therein, and an outer roller is mounted to each inner roller with a plurality of needle rollers engaged there-between.Type: GrantFiled: December 23, 2010Date of Patent: October 30, 2012Assignee: Hyundai Wia CorporationInventors: Jeong Hyun Cho, Dae Hwan Kim, In Sang Lee, Joung Sik Park, Sung Baek An, Seung Man Shin, Hwan Bum Kang
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METHODS OF BOOTING INFORMATION HANDLING SYSTEMS AND INFORMATION HANDLING SYSTEMS PERFORMING THE SAME
Publication number: 20120191964Abstract: A method of booting an information handling system including a volatile memory device to be selectively tested during a booting operation, the method comprising a step of reading current system configuration information from the information handling system, a step of comparing the current system configuration information with corresponding prestored system configuration information in a nonvolatile memory device, and a step of selectively performing a test for the volatile memory device according to a result of the comparison.Type: ApplicationFiled: December 8, 2011Publication date: July 26, 2012Inventors: JONG-MIN LEE, Hyung-Chan Choi, Hee-Joo Choi, Seung-Man Shin -
Patent number: 8051343Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.Type: GrantFiled: October 22, 2010Date of Patent: November 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
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Publication number: 20110159969Abstract: A tripod type constant velocity joint comprises a housing having three track grooves defined at trisected positions of the housing and extending in an axial direction, and a spider having three trunnions projectedly formed at trisected positions of the spider to be respectively inserted into the track, each trunnion having at least two polygonal surfaces at each of two opposing sides subjecting to a load. Inner rollers each has an inner surface of a concavely curved contour for receiving a corresponding trunnion therein, and an outer is mounted to each inner roller with a plurality of needle rollers engaged therebetween.Type: ApplicationFiled: December 23, 2010Publication date: June 30, 2011Applicant: HYUNDAI WIA CorporationInventors: JEONG HYUN CHO, Dae Hwan Kim, In Sang Lee, Joung Sik Park, Sung Baek An, Seung Man Shin, Hwan Bum Kang
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Publication number: 20110113296Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.Type: ApplicationFiled: October 22, 2010Publication date: May 12, 2011Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
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Patent number: 7874924Abstract: A tripod type constant velocity joint comprises a housing having three track grooves defined at trisected positions of the housing and extending in an axial direction, and a spider having three trunnions projectedly formed at trisected positions of the spider to be respectively inserted into the track grooves, each trunnion having at least two polygonal surfaces at each of two opposing sides subjecting to a load. Inner rollers each has an inner surface of a concavely curved contour for receiving a corresponding trunnion therein, and an outer is mounted to each inner roller with a plurality of needle rollers engaged there-between.Type: GrantFiled: October 29, 2007Date of Patent: January 25, 2011Assignee: Hyundai Wia CorporationInventors: Jeong Hyun Cho, Dae Hwan Kim, In Sang Lee, Joung Sik Park, Sung Baek An, Seung Man Shin, Hwan Bum Kang
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Publication number: 20110001467Abstract: A method of optimizing a driving voltage of an electronic device includes; iteratively varying the level of a driving voltage provided to the electronic device and performing an operation of the electronic device with each iteration until the operation fails, and then selecting as an operating level for the driving voltage, a level of the driving voltage for an iteration just prior to an iteration in which the operation fails.Type: ApplicationFiled: June 1, 2010Publication date: January 6, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung Chan CHOI, Hee Joo CHOI, Seung Man SHIN, Hui-Chung BYUN
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Patent number: 7849373Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.Type: GrantFiled: September 30, 2008Date of Patent: December 7, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
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Patent number: 7606110Abstract: A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.Type: GrantFiled: January 5, 2005Date of Patent: October 20, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: You-Keun Han, Hui-Chong Shin, Seung-Jin Seo, Byung-Se So, Young-Man Ahn, Seung-Man Shin, Jung-Kuk Lee, Ho-Suk Lee
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Patent number: 7539910Abstract: A memory module test system including at least one memory module. The at least one memory module includes a first hub and a plurality of semiconductor memory devices. The system includes a tester for testing the at least one memory module. A second hub is located between the first hub and the tester. The second hub is for converting a memory command and memory data output from the tester into packet data and transmits the packet data to the first hub. The second hub converts the packet data output from the first hub into memory data and transmits the memory data to the tester.Type: GrantFiled: July 28, 2004Date of Patent: May 26, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Man Ahn, Byung-Se So, Seung-Jin Seo, Seung-Man Shin
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Patent number: 7519873Abstract: Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least one bits stored in the first register may correspond one of the at least one test MRS codes stored in the second register.Type: GrantFiled: September 8, 2006Date of Patent: April 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Man Shin, Seung-Jin Seo, You-Keun Han, Hui-Chong Shin, Jong-Geon Lee, Kyung-Hee Han
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Publication number: 20090044062Abstract: A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module, providing the first data of the hub of the memory module to a first address of a memory, providing first expected data to the hub of the memory module, outputting second data stored at the first address of the memory to the hub of the memory module, and comparing the second data with the first expected data.Type: ApplicationFiled: September 30, 2008Publication date: February 12, 2009Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
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Patent number: 7487413Abstract: A memory module testing apparatus and method include a test slot adapted to receive a target memory module, wherein the target memory module includes a first memory unit to store information related to the target memory module. The memory module testing apparatus further includes a second memory unit adapted to store information related to a memory module, and a first switching unit adapted to selectively provide a driving signal to at least one of the first memory unit and the second memory unit.Type: GrantFiled: April 6, 2006Date of Patent: February 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-kuk Lee, Seung-jin Seo, You-keun Han, Seung-man Shin, Young-man Ahn
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Patent number: 7447954Abstract: A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module, providing the first data of the hub of the memory module to a first address of a memory, providing first expected data to the hub of the memory module, outputting second data stored at the first address of the memory to the hub of the memory module, and comparing the second data with the first expected data.Type: GrantFiled: May 2, 2005Date of Patent: November 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
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Patent number: 7343533Abstract: A hub for testing memory and methods thereof. The hub may include a test block a test block and a transparent mode block. The test block may be configured to generate a pseudo random pattern based on received memory control information and to write the pseudo random pattern to at least one of a plurality of memory devices in the first operating mode. The transparent mode block may be configured to receive the generated pseudo random pattern from the test block, to read the pseudo random pattern from the at least one of the plurality of memory devices in the first operating mode and to compare the generated pseudo random pattern with the read pseudo random pattern. Also, the hub may perform a transparent mode test on at least one memory device of a memory module with a pseudo random data pattern, the pseudo random data pattern based at least in part on memory control information received from a device not included within the memory module.Type: GrantFiled: October 28, 2005Date of Patent: March 11, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Kee-Hoon Lee, Seung-Man Shin