Abstract: A hub for testing memory and methods thereof. The hub may include a test block a test block and a transparent mode block. The test block may be configured to generate a pseudo random pattern based on received memory control information and to write the pseudo random pattern to at least one of a plurality of memory devices in the first operating mode. The transparent mode block may be configured to receive the generated pseudo random pattern from the test block, to read the pseudo random pattern from the at least one of the plurality of memory devices in the first operating mode and to compare the generated pseudo random pattern with the read pseudo random pattern. Also, the hub may perform a transparent mode test on at least one memory device of a memory module with a pseudo random data pattern, the pseudo random data pattern based at least in part on memory control information received from a device not included within the memory module.

Abstract: A test board for a high-frequency system level test: The test board includes a main board having through holes filled with a conductive material. These holes may be located at a portion of the main board from which an existing module socket has been removed. An interface board has surface mounted device (SMD) pads on front and rear surfaces. The SMD pads on the front surface of the interface board are connected with the SMD pads on the rear surface thereof through cross connection wiring within the interface board for a pin swap. The through holes of the main board are connected with the SMD pads on the rear surface of the interface board via iron cores fixed at a guide. A test module socket is mounted on surfaces of the SMD pads on the front surface of the interface board.

Abstract: A memory module and method thereof are provided. In the example method, a test signal may be applied to a plurality of memory chips included in the memory module. Output data from the plurality of memory chips may be received in response to the applied test signal. The received, output data may be divided into a plurality of groups. At least one of the plurality of groups may be selected in response to an output group selection signal. The at least one selected group may be output (e.g., to an external device). The example memory module may include a plurality of chips and a hub. The example memory module may be configured to perform the above-described example method.

Abstract: Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least one bits stored in the first register may correspond one of the at least one test MRS codes stored in the second register.

Abstract: A memory module testing apparatus that comprises a test slot adapted to receive a target memory module, wherein the target memory module comprises a first memory unit adapted to store information related to the target memory module, is disclosed. The memory module testing apparatus further comprises a second memory unit adapted to store information related to a memory module, and a first switching unit adapted to selectively provide a driving signal to at least one of the first memory unit and the second memory unit. A memory module testing method for the memory module testing apparatus is also disclosed.

Abstract: A hub for testing memory and methods thereof. The hub may include a test block a test block and a transparent mode block. The test block may be configured to generate a pseudo random pattern based on received memory control information and to write the pseudo random pattern to at least one of a plurality of memory devices in the first operating mode. The transparent mode block may be configured to receive the generated pseudo random pattern from the test block, to read the pseudo random pattern from the at least one of the plurality of memory devices in the first operating mode and to compare the generated pseudo random pattern with the read pseudo random pattern. Also, the hub may perform a transparent mode test on at least one memory device of a memory module with a pseudo random data pattern, the pseudo random data pattern based at least in part on memory control information received from a device not included within the memory module.

Abstract: In a method, a test pattern and an associated input mode may be received where the input mode may indicate a manner of applying the test pattern. An output test pattern is applied to at least one of a plurality of memory interface pins in accordance with the input mode. In a buffer, a test register may be configured to receive and store a test pattern and an associated input mode where the input mode may indicate a manner of applying the test pattern. The buffer may further include a test pattern generator configured to repeatedly generate an output test pattern based on the associated input mode.

Abstract: A method of testing an integrated circuit includes providing a bank access sequence received to a register in the integrated circuit, generating a test pattern sequence based on the bank access sequence, and performing a Built-In Self Test (BIST) operation on the integrated circuit based on the generated test pattern sequence.

Abstract: A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.

Abstract: A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module, providing the first data of the hub of the memory module to a first address of a memory, providing first expected data to the hub of the memory module, outputting second data stored at the first address of the memory to the hub of the memory module, and comparing the second data with the first expected data.

Abstract: A method of entering memory module mounted on a memory system or a plurality of memories mounted on the memory module into a test mode, and a first register and a second register for performing the method are introduced. Each of the memory manufacturers provides a different MRS code for entering the memory into the test mode and a different method of entering the memory into the test mode from one another. As a result, the number of the test MRS is stored in the first register for controlling the memory, and the test MRS codes are programmed into the second register. Additionally, each of the bits stored in the first register used for determining the number of the test MRS corresponds to each of the second registers that store a corresponding test MRS code, respectively.

Abstract: A test board for a high-frequency system level test: The test board includes a main board having through holes filled with a conductive material. These holes may be located at a portion of the main board from which an existing module socket has been removed. An interface board has surface mounted device (SMD) pads on front and rear surfaces. The SMD pads on the front surface of the interface board are connected with the SMD pads on the rear surface thereof through cross connection wiring within the interface board for a pin swap. The through holes of the main board are connected with the SMD pads on the rear surface of the interface board via iron cores fixed at a guide. A test module socket is mounted on surfaces of the SMD pads on the front surface of the interface board.

Abstract: A memory module test system including at least one memory module. The at least one memory module includes a first hub and a plurality of semiconductor memory devices. The system includes a tester for testing the at least one memory module. A second hub is located between the first hub and the tester. The second hub is for converting a memory command and memory data output from the tester into packet data and transmits the packet data to the first hub. The second hub converts the packet data output from the first hub into memory data and transmits the memory data to the tester.