Patents by Inventor Seung Mi Lee

Seung Mi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9657119
    Abstract: The present invention relates to a preparation method of a highly active supported metallocene catalyst which can prepare a polyolefin of high bulk density. More specifically, the present invention provides a method of preparing the supported metallocene catalyst in which one or more metallocene catalysts are loaded on the silica carrier of which the inside is penetrated by more cocatalyst than the prior art and the outside is attached with a substantial amount of the cocatalyst. The catalyst according to the present invention can prepare a polyolefin polymer with improved bulk density and efficiency while maintaining its highly active catalytic characteristic.
    Type: Grant
    Filed: November 28, 2014
    Date of Patent: May 23, 2017
    Assignee: LG Chem, Ltd.
    Inventors: Seung Mi Lee, Yi Young Choi, Ki Soo Lee, Eun Kyoung Song, Heon Yong Kwon, Min Seok Cho, Dae Sik Hong, Hyun Jee Kwon, Yu Taek Sung, Dong Hoon Jeong
  • Patent number: 9659828
    Abstract: A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 23, 2017
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Beom-Yong Kim, Seung-Mi Lee
  • Patent number: 9548304
    Abstract: A method for fabricating a semiconductor device includes forming an NMOS region and a PMOS region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the PMOS region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the NMOS region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: January 17, 2017
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Se-Aug Jang, Seung-Mi Lee, Hyung-Chul Kim
  • Publication number: 20160357371
    Abstract: Disclosed herein are a schedule management terminal and method. The schedule management terminal includes a display unit, an input unit, and a control unit. The display unit may display a user interface including a period display region, in which a continuous period is divided into intervals, and one or more event buttons. The input unit may receive user input including a selection, a dragging or a dropping for the user interface that is displayed by the display unit. When receiving user input adapted to select a part of the event buttons via the input unit and drag and drop the selected event button on a desired interval of the period display region, the control unit may generate event information corresponding to the selected event button for the desired interval.
    Type: Application
    Filed: August 18, 2016
    Publication date: December 8, 2016
    Inventor: Seung Mi LEE
  • Publication number: 20160304637
    Abstract: The present invention relates to a preparation method of a highly active supported metallocene catalyst which can prepare a polyolefin of high bulk density. More specifically, the present invention provides a method of preparing the supported metallocene catalyst in which one or more metallocene catalysts are loaded on the silica carrier of which the inside is penetrated by more cocatalyst than the prior art and the outside is attached with a substantial amount of the cocatalyst. The catalyst according to the present invention can prepare a polyolefin polymer with improved bulk density and efficiency while maintaining its highly active catalytic characteristic.
    Type: Application
    Filed: November 28, 2014
    Publication date: October 20, 2016
    Applicant: LM CHEM, LTD.
    Inventors: Seung Mi LEE, Yi Young CHOI, Ki Soo LEE, Eun Kyoung SONG, Heon Yong KWON, Min Seok CHO, Dae Sik HONG, Hyun Jee KWON, Yu Taek SUNG, Dong Hoon JEONG
  • Patent number: 9431402
    Abstract: A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: August 30, 2016
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yun-Hyuck Ji, Kwan-Woo Do, Beom-Yong Kim, Seung-Mi Lee, Woo-Young Park
  • Patent number: 9406678
    Abstract: A method of fabricating a semiconductor device. A substrate (PMOS/NMOS regions) is prepared. A high-k dielectric layer is formed over the substrate. A threshold voltage modulation layer is formed over the dielectric layer of the NMOS region. A first work function layer is formed over the threshold voltage modulation layer and the dielectric layer of the PMOS region. An oxidation suppressing layer is formed over the first work function layer of the NMOS region. A second work function layer is formed over the oxidation suppressing layer and the first work function layer of the PMOS region. A first gate stack including the dielectric layer, the first work function layer and the second work function layer is formed over the PMOS region. A second gate stack including the dielectric layer, the threshold voltage modulation layer, the first work function layer and the oxidation suppressing layer is formed over NMOS region.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 2, 2016
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Moon-Sig Joo, Se-Aug Jang, Seung-Mi Lee, Hyung-Chul Kim
  • Publication number: 20160211183
    Abstract: A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.
    Type: Application
    Filed: March 30, 2016
    Publication date: July 21, 2016
    Inventors: Yun-Hyuck JI, Beom-Yong KIM, Seung-Mi LEE
  • Patent number: 9379023
    Abstract: A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first region and a second gate stack structure containing a second effective work function adjust species is formed over the second region. A channel region is formed under the first gate stack structure and contains a threshold voltage adjust species.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: June 28, 2016
    Assignee: SK Hynix Inc.
    Inventors: Seung-Mi Lee, Yun-Hyuck Ji
  • Publication number: 20160148934
    Abstract: A method for fabricating a semiconductor device includes forming an NMOS region and a PMOS region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the PMOS region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the NMOS region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively.
    Type: Application
    Filed: February 1, 2016
    Publication date: May 26, 2016
    Inventors: Yun-Hyuck JI, Se-Aug JANG, Seung-Mi LEE, Hyung-Chul KIM
  • Patent number: 9337108
    Abstract: A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: May 10, 2016
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Beom-Yong Kim, Seung-Mi Lee
  • Patent number: 9318595
    Abstract: A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: April 19, 2016
    Assignee: SK Hynix Inc.
    Inventors: Seung-Mi Lee, Yun-Hyuck Ji, Beom-Yong Kim, Bong-Seok Jeon
  • Patent number: 9281310
    Abstract: A method for fabricating a semiconductor device includes forming an NMOS region and a PMOS region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the PMOS region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the NMOS region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 8, 2016
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Se-Aug Jang, Seung-Mi Lee, Hyung-Chul Kim
  • Patent number: 9230963
    Abstract: A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate; forming a metal containing layer, containing an effective work function adjust species, over the gate dielectric layer; forming an anti-reaction layer over the metal containing layer; increasing an amount of the effective work function adjust species contained in the metal containing layer; and forming, on the substrate, a gate stack by etching the anti-reaction layer, the metal containing layer, and the gate dielectric layer.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: January 5, 2016
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Se-Aug Jang, Seung-Mi Lee, Hyung-Chul Kim
  • Patent number: 9189105
    Abstract: Disclosed herein is a touch sensor, including: a window; a transparent substrate having a first electrode part formed on one surface thereof; and a first adhesive layer allowing the window and one surface of the transparent substrate to adhere to each other, wherein a first protrusion part is formed on an edge of one surface of the transparent substrate.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 17, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hee Jin Park, Ji Hyuk Lim, Seung Mi Lee, Suk Jin Ham
  • Patent number: 9159779
    Abstract: A method for fabricating a semiconductor device includes forming a metal layer over a substrate, forming a capping layer over the metal layer, and densifying the metal layer through a heat treatment.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 13, 2015
    Assignee: SK Hynix Inc.
    Inventors: Beom-Yong Kim, Yun-Hyuck Ji, Seung-Mi Lee
  • Publication number: 20150263119
    Abstract: A semiconductor device includes a gate stacked structure including a gate dielectric layer over a semiconductor substrate, a metal layer formed over the gate dielectric layer, and a capping layer formed over the metal layer, where the capping layer includes a chemical element with a higher concentration at an interface between the capping layer and the metal layer than another region of the capping layer and the chemical element is operable to control an effective work function (eWF) of the gate stacked structure.
    Type: Application
    Filed: May 26, 2015
    Publication date: September 17, 2015
    Inventors: Woo-Young PARK, Kee-Jeung LEE, Yun-Hyuck JI, Seung-Mi LEE
  • Patent number: 9125687
    Abstract: According to the present invention, an amniotic fluid collector is configured so as to be inserted and positioned inside the vagina of a birthing mother in order to collect amniotic fluid from the womb of the birthing mother. In particular, the amniotic fluid collector of the present invention comprises: a receiving member, in the side of which an opening is defined, which is inserted into the vagina of the birthing mother and which has a receptacle defined therein for receiving the amniotic fluid; and a positioning portion for positioning the receiving member inside the vagina. Thus, the effects of alleviating pain and psychological anxiety of a birthing mother and eliminating the danger of the occurrence of complications can be achieved, as well as those of easily and smoothly collecting amniotic fluid from the womb of the birthing mother.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: September 8, 2015
    Assignee: SNU R&DB FOUNDATION
    Inventors: Bo Hyun Yoon, Chan Wook Park, Seung Mi Lee, Joong Shin Park
  • Publication number: 20150206805
    Abstract: A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first region and a second gate stack structure containing a second effective work function adjust species is formed over the second region. A channel region is formed under the first gate stack structure and contains a threshold voltage adjust species.
    Type: Application
    Filed: March 26, 2015
    Publication date: July 23, 2015
    Inventors: Seung-Mi LEE, Yun-Hyuck JI
  • Publication number: 20150137257
    Abstract: A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate; forming a metal containing layer, containing an effective work function adjust species, over the gate dielectric layer; forming an anti-reaction layer over the metal containing layer; increasing an amount of the effective work function adjust species contained in the metal containing layer; and forming, on the substrate, a gate stack by etching the anti-reaction layer, the metal containing layer, and the gate dielectric layer.
    Type: Application
    Filed: January 27, 2015
    Publication date: May 21, 2015
    Inventors: Yun-Hyuck JI, Se-Aug JANG, Seung-Mi LEE, Hyung-Chul KIM