Patents by Inventor Seung Mi Lee

Seung Mi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9034747
    Abstract: A semiconductor device includes a gate insulation layer formed over a substrate and having a high dielectric constant, a gate electrode formed over the gate insulation layer and a work function control layer formed between the substrate and the gate insulation layer and inducing a work function shift of the gate electrode.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: May 19, 2015
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Tae-Yoon Kim, Seung-Mi Lee, Woo-Young Park
  • Publication number: 20150129973
    Abstract: A method for fabricating a semiconductor device includes forming an NMOS region and a PMOS region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the PMOS region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the NMOS region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively.
    Type: Application
    Filed: March 14, 2014
    Publication date: May 14, 2015
    Applicant: SK hynix Inc.
    Inventors: Yun-Hyuck JI, Se-Aug JANG, Seung-Mi LEE, Hyung-Chul KIM
  • Publication number: 20150123167
    Abstract: A method of fabricating a semiconductor device. A substrate (PMOS/NMOS regions) is prepared. A high-k dielectric layer is formed over the substrate. A threshold voltage modulation layer is formed over the dielectric layer of the NMOS region. A first work function layer is formed over the threshold voltage modulation layer and the dielectric layer of the PMOS region. An oxidation suppressing layer is formed over the first work function layer of the NMOS region. A second work function layer is formed over the oxidation suppressing layer and the first work function layer of the PMOS region. A first gate stack including the dielectric layer, the first work function layer and the second work function layer is formed over the PMOS region. A second gate stack including the dielectric layer, the threshold voltage modulation layer, the first work function layer and the oxidation suppressing layer is formed over NMOS region.
    Type: Application
    Filed: March 14, 2014
    Publication date: May 7, 2015
    Applicant: SK hynix Inc.
    Inventors: Yun-Hyuck JI, Moon-Sig JOO, Se-Aug JANG, Seung-Mi LEE, Hyung-Chul KIM
  • Patent number: 9018710
    Abstract: A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first region and a second gate stack structure containing a second effective work function adjust species is formed over the second region. A channel region is formed under the first gate stack structure and contains a threshold voltage adjust species.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Seung-Mi Lee, Yun-Hyuck Ji
  • Patent number: 8962463
    Abstract: A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate; forming a metal containing layer, containing an effective work function adjust species, over the gate dielectric layer; forming an anti-reaction layer over the metal containing layer; increasing an amount of the effective work function adjust species contained in the metal containing layer; and forming, on the substrate, a gate stack by etching the anti-reaction layer, the metal containing layer, and the gate dielectric layer.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: February 24, 2015
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Se-Aug Jang, Seung-Mi Lee, Hyung-Chul Kim
  • Patent number: 8962437
    Abstract: A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and the second silicon layer.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: February 24, 2015
    Assignee: SK Hynix Inc.
    Inventors: Beom-Yong Kim, Kee-Jeung Lee, Yun-Hyuck Ji, Seung-Mi Lee, Jae-Hyoung Koo, Kwan-Woo Do, Kyung-Woong Park, Ji-Hoon Ahn, Woo-Young Park
  • Publication number: 20140352413
    Abstract: Disclosed herein is a moisture transmission testing instrument of measuring moisture transmission of an electronic material, the moisture transmission testing instrument including: a moisture supplying part having an opened upper portion and having water stored therein; a sample support part stacked on the moisture supplying part so as to be communicated with the moisture supplying part and having a sample seated on an upper side thereof; and a moisture collecting part stacked on the sample support part so as to be communicated with the sample support part and having a dehumidifying agent installed therein.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 4, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hee Jin PARK, Seung Mi LEE, Suk Jin HAM
  • Publication number: 20140203337
    Abstract: A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process.
    Type: Application
    Filed: January 27, 2014
    Publication date: July 24, 2014
    Applicant: SK hynix Inc.
    Inventors: Seung-Mi LEE, Yun-Hyuck JI, Beom-Yong KIM, Bong-Seok JEON
  • Publication number: 20140187030
    Abstract: A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate; forming a metal containing layer, containing an effective work function adjust species, over the gate dielectric layer; forming an anti-reaction layer over the metal containing layer; increasing an amount of the effective work function adjust species contained in the metal containing layer; and forming, on the substrate, a gate stack by etching the anti-reaction layer, the metal containing layer, and the gate dielectric layer.
    Type: Application
    Filed: March 18, 2013
    Publication date: July 3, 2014
    Applicant: SK HYNIX INC.
    Inventors: Yun-Hyuck JI, Se-Aug JANG, Seung-Mi LEE, Hyung-Chul KIM
  • Publication number: 20140183649
    Abstract: A semiconductor device includes an N-channel transistor configured to have a first gate dielectric layer, a first metal containing gate electrode and a dipole forming layer, wherein the first metal containing gate electrode is formed on the first gate dielectric layer, and the dipole forming layer is formed on an interface of the first gate dielectric layer and the first metal containing gate electrode, and a P-channel transistor configured to have a channel region, a second gate dielectric layer and a second metal containing gate electrode, wherein the channel region has threshold voltage adjusting species, the second gate dielectric layer is formed on the channel region, and the second metal containing gate electrode has effective work function adjusting species of the second gate dielectric layer.
    Type: Application
    Filed: March 16, 2013
    Publication date: July 3, 2014
    Applicant: SK HYNIX INC.
    Inventors: Seung-Mi LEE, Yun-Hyuck JI
  • Publication number: 20140183651
    Abstract: A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first region and a second gate stack structure containing a second effective work function adjust species is formed over the second region A channel region is formed under the first gate stack structure and contains a threshold voltage adjust species.
    Type: Application
    Filed: March 18, 2013
    Publication date: July 3, 2014
    Applicant: SK HYNIX INC.
    Inventors: Seung-Mi LEE, Yun-Hyuck JI
  • Publication number: 20140176506
    Abstract: Disclosed herein is a touch sensor, including: a window; a transparent substrate having a first electrode part formed on one surface thereof; and a first adhesive layer allowing the window and one surface of the transparent substrate to adhere to each other, wherein a first protrusion part is formed on an edge of one surface of the transparent substrate.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 26, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hee Jin PARK, Ji Hyuk Lim, Seung Mi Lee, Suk Jin Ham
  • Publication number: 20140162448
    Abstract: A semiconductor device includes a gate insulation layer formed over a substrate and having a high dielectric constant, a gate electrode formed over the gate insulation layer and a work function control layer formed between the substrate and the gate insulation layer and inducing a work function shift of the gate electrode.
    Type: Application
    Filed: February 14, 2014
    Publication date: June 12, 2014
    Applicant: SK hynix Inc.
    Inventors: Yun-Hyuck JI, Tae-Yoon KIM, Seung-Mi LEE, Woo-Young PARK
  • Patent number: 8673754
    Abstract: A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: March 18, 2014
    Assignee: SK hynix Inc.
    Inventors: Seung-Mi Lee, Yun Hyuck Ji, Beom-Yong Kim, Bong-Seok Jeon
  • Patent number: 8653611
    Abstract: A semiconductor device includes a gate insulation layer formed over a substrate and having a high dielectric constant, a gate electrode formed over the gate insulation layer and a work function control layer formed between the substrate and the gate insulation layer and inducing a work function shift of the gate electrode.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: February 18, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yun-Hyuck Ji, Tae-Yoon Kim, Seung-Mi Lee, Woo-Young Park
  • Publication number: 20140004679
    Abstract: A method for fabricating a semiconductor device includes forming a metal layer over a substrate, forming a capping layer over the metal layer, and densifying the metal layer through a heat treatment.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 2, 2014
    Inventors: Beom-Yong KIM, Yun-Hyuck Ji, Seung-Mi Lee
  • Publication number: 20130240957
    Abstract: A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process.
    Type: Application
    Filed: June 12, 2012
    Publication date: September 19, 2013
    Inventors: Seung-Mi LEE, Yun Hyuck JI, Beom-Yong KIM, Bong-Seok JEON
  • Publication number: 20130244394
    Abstract: A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and the second silicon layer.
    Type: Application
    Filed: June 12, 2012
    Publication date: September 19, 2013
    Inventors: Beom-Yong KIM, Kee-Jeung LEE, Yun-Hyuck JI, Seung-Mi LEE, Jae-Hyoung KOO, Kwan-Woo DO, Kyung-Woong PARK, Ji-Hoon AHN, Woo-Young PARK
  • Publication number: 20130161710
    Abstract: A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.
    Type: Application
    Filed: May 10, 2012
    Publication date: June 27, 2013
    Inventors: Yun-Hyuck Ji, Kwan-Woo Do, Beom-Yong Kim, Seung-Mi Lee, Woo-Young Park
  • Publication number: 20130105905
    Abstract: A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.
    Type: Application
    Filed: December 29, 2011
    Publication date: May 2, 2013
    Inventors: Yun-Hyuck JI, Beom-Yong Kim, Seung-Mi Lee