Patents by Inventor Seung Min Song
Seung Min Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10347718Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.Type: GrantFiled: January 23, 2018Date of Patent: July 9, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jung Gil Yang, Dong Il Bae, Chang Woo Sohn, Seung Min Song, Dong Hun Lee
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Publication number: 20190157444Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.Type: ApplicationFiled: August 28, 2018Publication date: May 23, 2019Inventors: Jung-Gil Yang, Beom-Jin Park, Seung-Min Song, Geum-Jong Bae, Dong-Il Bae
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Publication number: 20190115424Abstract: A semiconductor device including a transistor disposed on a first region of a substrate, the transistor including source/drain regions, a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate while connecting the source/drain regions, respectively, a gate electrode surrounding each of the plurality of channel layers, and a gate insulator between the gate electrode and the plurality of channel layers; and a non-active component disposed on a second region of the substrate, the non-active component including a fin structure including an a plurality of first semiconductor patterns alternately stacked with a plurality of second semiconductor patterns, an epitaxial region adjacent to the fin structure, a non-active electrode intersecting the fin structure, and a blocking insulation film between the non-active electrode and the fin structure.Type: ApplicationFiled: April 27, 2018Publication date: April 18, 2019Inventors: Woo Seok PARK, Seung Min SONG, Jung Gil YANG, Geum Jong BAE, Dong Il BAE
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Publication number: 20190096996Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided.Type: ApplicationFiled: August 1, 2018Publication date: March 28, 2019Inventors: Seung-Min SONG, Woo-Seok PARK, Jung-Gil YANG, Geum-Jong BAE, Dong-Il Bae
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Patent number: 10243040Abstract: A semiconductor device including a transistor disposed on a first region of a substrate, the transistor including source/drain regions, a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate while connecting the source/drain regions, respectively, a gate electrode surrounding each of the plurality of channel layers, and a gate insulator between the gate electrode and the plurality of channel layers; and a non-active component disposed on a second region of the substrate, the non-active component including a fin structure including an a plurality of first semiconductor patterns alternately stacked with a plurality of second semiconductor patterns, an epitaxial region adjacent to the fin structure, a non-active electrode intersecting the fin structure, and a blocking insulation film between the non-active electrode and the fin structure.Type: GrantFiled: April 27, 2018Date of Patent: March 26, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo Seok Park, Seung Min Song, Jung Gil Yang, Geum Jong Bae, Dong Il Bae
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Publication number: 20190088789Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.Type: ApplicationFiled: October 16, 2018Publication date: March 21, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Min SONG, Woo Seok PARK, Geum Jong BAE, Dong Il BAE, Jung Gil YANG
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Publication number: 20190067490Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.Type: ApplicationFiled: February 20, 2018Publication date: February 28, 2019Inventors: Jung Gil Yang, Woo Seok PARK, Dong Chan SUH, Seung Min SONG, Geum Jong BAE, Dong II BAE
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Patent number: 10204983Abstract: A semiconductor device may include a substrate, a first nanowire, a gate electrode, a first gate spacer, a second gate spacer, a source/drain and a spacer connector. The first nanowire may be extended in a first direction and spaced apart from the substrate. The gate electrode may surround a periphery of the first nanowire, and extend in a second direction intersecting the first direction, and include first and second sidewalls opposite to each other. The first gate spacer may be formed on the first sidewall of the gate electrode. The first nanowire may pass through the first gate spacer. The second gate spacer may be formed on the second sidewall of the gate electrode. The first nanowire may pass through the second gate spacer. The source/drain may be disposed on at least one side of the gate electrode and connected with the first nanowire. The spacer connector may be disposed between the first nanowire and the substrate.Type: GrantFiled: February 28, 2017Date of Patent: February 12, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Dae Suk, Seung Min Song, Geum Jong Bae
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Patent number: 10181510Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.Type: GrantFiled: October 6, 2017Date of Patent: January 15, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Gil Yang, Seung Min Song, Sung Min Kim, Woo Seok Park, Geum Jong Bae, Dong Il Bae
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Patent number: 10128379Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.Type: GrantFiled: July 12, 2017Date of Patent: November 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Min Song, Woo Seok Park, Geum Jong Bae, Dong Il Bae, Jung Gil Yang
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Publication number: 20180261668Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.Type: ApplicationFiled: October 6, 2017Publication date: September 13, 2018Inventors: JUNG GIL YANG, SEUNG MIN SONG, SUNG MIN KIM, WOO SEOK PARK, GEUM JONG BAE, DONG IL BAE
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Publication number: 20180190829Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.Type: ApplicationFiled: July 12, 2017Publication date: July 5, 2018Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Min SONG, Woo Seok PARK, Geum Jong BAE, Dong Il BAE, Jung Gil YANG
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Patent number: 10014393Abstract: A method of manufacturing semiconductor device includes forming a plurality of sacrificial layers and a plurality of semiconductor layers repeatedly and alternately stacked on a substrate, partially removing the sacrificial layers, forming spacers in removed regions of the sacrificial layers, and replacing remaining portions of the sacrificial layers with a gate electrode. Each of the sacrificial layers includes first portions disposed adjacent to the plurality of semiconductor layers and a second portions disposed between the first portions. The second portion having a different composition from the first portions.Type: GrantFiled: November 25, 2016Date of Patent: July 3, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Min Song, Dong Chan Suh, Jung Gil Yang, Geum Jong Bae, Woo Bin Song
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Publication number: 20180175035Abstract: A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode.Type: ApplicationFiled: December 4, 2017Publication date: June 21, 2018Inventors: JUNG-GIL YANG, GEUM-JONG BAE, DONG-IL BAE, SEUNG-MIN SONG, WOO-SEOK PARK
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Publication number: 20180158908Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.Type: ApplicationFiled: January 23, 2018Publication date: June 7, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Jung Gil YANG, Dong II BAE, Chang Woo SOHN, Seung Min SONG, Dong Hun LEE
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Publication number: 20180090569Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.Type: ApplicationFiled: March 20, 2017Publication date: March 29, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Jung Gil YANG, Dong ll BAE, Chang Woo SOHN, Seung Min SONG, Dong Hun LEE
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Patent number: 9929235Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.Type: GrantFiled: March 20, 2017Date of Patent: March 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Gil Yang, Dong Il Bae, Chang Woo Sohn, Seung Min Song, Dong Hun Lee
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Publication number: 20170358665Abstract: A method of manufacturing semiconductor device includes forming a plurality of sacrificial layers and a plurality of semiconductor layers repeatedly and alternately stacked on a substrate, partially removing the sacrificial layers, forming spacers in removed regions of the sacrificial layers, and replacing remaining portions of the sacrificial layers with a gate electrode. Each of the sacrificial layers includes first portions disposed adjacent to the plurality of semiconductor layers and a second portions disposed between the first portions. The second portion having a different composition from the first portions.Type: ApplicationFiled: November 25, 2016Publication date: December 14, 2017Inventors: SEUNG MIN SONG, DONG CHAN SUH, JUNG GIL YANG, GEUM JONG BAE, WOO BIN SONG
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Publication number: 20170256608Abstract: A semiconductor device may include a substrate, a first nanowire, a gate electrode, a first gate spacer, a second gate spacer, a source/drain and a spacer connector. The first nanowire may be extended in a first direction and spaced apart from the substrate. The gate electrode may surround a periphery of the first nanowire, and extend in a second direction intersecting the first direction, and include first and second sidewalls opposite to each other. The first gate spacer may be formed on the first sidewall of the gate electrode. The first nanowire may pass through the first gate spacer. The second gate spacer may be formed on the second sidewall of the gate electrode. The first nanowire may pass through the second gate spacer. The source/drain may be disposed on at least one side of the gate electrode and connected with the first nanowire. The spacer connector may be disposed between the first nanowire and the substrate.Type: ApplicationFiled: February 28, 2017Publication date: September 7, 2017Inventors: Sung Dae SUK, Seung Min SONG, Geum Jong BAE
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Publication number: 20140224822Abstract: A paper cap having an improved structure to prevent a skirt part from being deformed and the paper cap from being easily separated from a container is disclosed. The paper cap includes a circular plane part for covering an upper portion of a container and a skirt part extending downward from an edge of the plane part. The skirt part has a circumference groove fitted into a curling part of the paper cup and a ring-shaped reinforcing groove on which a plurality of uneven wrinkles are formed in a length direction and which is formed along the inner circumference surface at a position spaced apart from the circumference groove.Type: ApplicationFiled: September 19, 2012Publication date: August 14, 2014Applicant: SJP CO., LTD.Inventor: Seung Min Song