Abstract: The present invention relates to a method for preparing boehmite and ?-alumina with high surface area, and more particularly, to a method comprising hydrolysis of aluminum alkoxides to produce boehmite and calcination to produce ?-alumina, wherein an alcohol is used as a reaction solvent and a small amount of water and a particular organic carboxylic acid are added so that not only the reaction solvent is easily recovered and energy required for drying is significantly reduced but also it provides boehmite having nano-sized particles, high surface area, and high purity. Further, the prepared ?-alumina may be suitable for high value added industrial applications such as manufacture of adsorbents, catalysts, catalyst supports and chromatography materials.

Abstract: A digital transmission circuit and method providing selectable power consumption via single-ended or differential operation improves the flexibility of an interface while reducing power consumption when possible. A differential path is provided through the transmitter output driver stages and portions are selectively disabled when the transmission circuit is in a lower-power operating mode. A single-ended to differential converter circuit can be used to construct a differential signal for output to the final driver stage. The selection of power mode can be made via feedback from a channel quality measurement unit or may be hardwired or selected under programmatic control. The longer delay or skew of the lower-power single-ended mode is compensated for by the relaxed requirements of the channel when conditions permit the use of the lower-power single-ended mode.

Abstract: Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.

Abstract: An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and t

Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

Abstract: A coil-driving apparatus of an electro magnetic contactor is disclosed, which replaces the main units in an analog scheme with those in a digital scheme using a PWM controller of low power consumption to reduce the number of the analog components, minimize power consumption, and controls a constant voltage that flows on the coil by receiving the feedback current flowing on the coil, whereby error and defect generation rates are reduced, and deterioration and burning of components are prevented.

Abstract: Disclosed herein are a desulfurizing agent for removing organic sulfur compounds, a preparation method thereof, and a method for removing organic sulfur compounds using the same. The desulfurizing agent consists of a copper-zinc-aluminum complex free of alkaline metal, with a large surface area. When being contacted with organic sulfur compounds, such as t-butylmercaptan, tetrahydrothiophene, dimethylsulfide, etc., the desulfurizing agent exhibits excellent desulfurization ability and is not de-graded especially at high temperatures as high as 150˜350° C.

Abstract: A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Abstract: A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing power consumption when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Abstract: A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Abstract: Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.

Abstract: An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate c

Abstract: A liquid crystal display and method for driving the liquid crystal display are provided.

Abstract: Provided are a paraelectric thin film structure and a high frequency tunable device with the paraelectric thin film structure. The paraelectric thin film structure has a large dielectric constant tuning rate and a low dielectric loss at a high frequency. The paraelectric thin film structure includes a perovskite ABO3 type paraelectric film formed on an oxide single crystal substrate. The paraelectric film is formed of a material selected from Ba(Zrx,Ti1-x)O3, Ba(Hfy,Ti1-y)O3, or Ba(Snz,Ti1-z)O3. Instead of the paraelectric film, the paraelectric thin film structure may include a compositionally graded paraelectric film having at least two paraelectric films formed of the selected material by varying the composition ratio x, y, or z. A high-frequency/phase tunable device employing the paraelectric thin film structure can have improved microwave characteristics and high-speed, low-power-consuming, low-cost characteristics.

Abstract: Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.

Abstract: Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.

Abstract: An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

Abstract: Disclosed is a method for manufacturing a semiconductor device using an immersion lithography process comprising rapidly accelerating the rotation of a wafer after exposing and before developing steps to remove an immersion lithography solution, thereby effectively reducing water mark defects.

Abstract: Disclosed herein is a top anti-reflective coating polymer represented by Formula 1, below: wherein R1 and R2 are independently hydrogen, fluoro, methyl or fluoromethyl; R3 is a C1-10 hydrocarbon or a C1-10 hydrocarbon in which the hydrogen atoms are partly replaced by fluorine atoms; and a, b and c, representing the mole fraction of each monomer, are in the range between 0.05 and 0.9. Because a top anti-reflective coating formed using the anti-reflective coating polymer of Formula 1 is not soluble in water, it can be applied to immersion lithography using water as a medium for a light source. In addition, because the top anti-reflective coating can reduce the reflectance from an underlying layer, the uniformity of CD is improved, thus enabling the formation of an ultra fine pattern.

Abstract: An apparatus for inspecting an alignment film and a method for fabricating a liquid crystal display device using the same are disclosed. By changing a spraying structure of a steam inspecting unit to check whether an alignment film is defective or not, a water splash phenomenon can be prevented and spraying can be performed uniformly on a large-scale glass. The apparatus for inspecting an alignment film comprises a first steam generating unit for generating first steam; a second steam generating unit for generating second steam by using the first steam as a heat source; and a steam spraying unit for spraying the second steam onto a substrate of a substrate to inspect an alignment film formed on the substrate.