Abstract: A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled.

Abstract: A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer.

Abstract: A dielectric structure disposed between a floating gate and a control gate of a flash memory device includes: a first dielectric layer; a third dielectric layer having a k-dielectric constant substantially the same as that of the first dielectric layer; and a second dielectric layer disposed between the first dielectric layer and the third dielectric layer, having a greater k-dielectric constant than that of the first and third dielectric layers and formed by alternately and repeatedly stacking a plurality of aluminum oxide (Al2O3) layers and a plurality of zirconium oxide (ZrO2) layers.

Abstract: A dielectric structure disposed between a floating gate and a control gate of a flash memory device includes: a first dielectric layer; a third dielectric layer having a k-dielectric constant substantially the same as that of the first dielectric layer; and a second dielectric layer disposed between the first dielectric layer and the third dielectric layer, having a greater k-dielectric constant than that of the first and third dielectric layers and formed by alternately and repeatedly stacking a plurality of aluminum oxide (Al2O3) layers and a plurality of zirconium oxide (ZrO2) layers.

Abstract: Disclosed are a semiconductor device with dual gate dielectric layers and a method for fabricating the same. The semiconductor device includes: a silicon substrate divided into a cell region where NMOS transistors are formed and a peripheral region where NMOS and PMOS transistors are formed; a targeted silicon oxide layer formed on the silicon substrate in the cell region; an oxynitride layer formed on the silicon substrate in the peripheral region; a first gate structure formed in the cell region; a second gate structure formed on the oxynitride layer in an NMOS region of the peripheral region; and a third gate structure formed on the oxynitride layer in a PMOS region of the peripheral region.

Abstract: A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled.

Abstract: Disclosed herein is a nonvolatile memory device that includes a substrate, a tunneling layer over the substrate, a charge trapping layer over the tunneling layer, an insulating layer for improving retention characteristics over the charge trapping layer, a blocking layer over the insulating layer, and a control gate electrode over the blocking layer. Also disclosed herein is a method of making the device.

Abstract: A non-volatile memory device comprises a substrate, a tunneling layer over the substrate, a charge trapping layer comprising a stoichiometric silicon nitride layer and a silicon-rich silicon nitride layer over the tunneling layer, a blocking layer over the charge trapping layer, and a control gate electrode over the blocking layer.

Abstract: A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.

Abstract: A dielectric structure disposed between a floating gate and a control gate of a flash memory device includes: a first dielectric layer; a third dielectric layer having a k-dielectric constant substantially the same as that of the first dielectric layer; and a second dielectric layer disposed between the first dielectric layer and the third dielectric layer, having a greater k-dielectric constant than that of the first and third dielectric layers and formed by alternately and repeatedly stacking a plurality of aluminum oxide (Al2O3) layers and a plurality of zirconium oxide (ZrO2) layers.

Abstract: A microwave oven includes a door. The door includes a door unit for selectively opening/closing a cooking chamber and a control unit, for controlling an operation of the microwave oven, is arranged at a predetermined part of the door unit.

Abstract: A gate electrode with a double diffusion barrier and a fabrication method of a semiconductor device including the same are provided. The gate electrode of a semiconductor device includes: a silicon electrode; a double diffusion barrier formed on the silicon electrode and including at least a crystalline tungsten nitride-based layer; and a metal electrode formed on the double diffusion barrier.

Abstract: Disclosed herein is a door hinge structure for a refrigerator.

Abstract: Disclosed are a synthetic resin film envelope and a cultivating method for clean agricultural products. The synthetic resin film envelope is formed with a double-layer sectional structure having a thickness of about 0.02 to 0.1 mm and includes 60 to 90 weight percent of polypropylene resin having a melt index of 3 to 10 g/min at a temperature of 185° C., 1 to 20 weight percent of an antifogging agent, 1 to 10 weight percent of an antistatic agent, and 1 to 10 weight percent of white carbon.

Abstract: Disclosed are a semiconductor device with dual gate dielectric layers and a method for fabricating the same. The semiconductor device includes: a silicon substrate divided into a cell region where NMOS transistors are formed and a peripheral region where NMOS and PMOS transistors are formed; a targeted silicon oxide layer formed on the silicon substrate in the cell region; an oxynitride layer formed on the silicon substrate in the peripheral region; a first gate structure formed in the cell region; a second gate structure formed on the oxynitride layer in an NMOS region of the peripheral region; and a third gate structure formed on the oxynitride layer in a PMOS region of the peripheral region.

Abstract: A microwave oven includes a door. The door includes a door unit for selectively opening/closing a cooking chamber and a control unit, for controlling an operation of the microwave oven, is arranged at a predetermined part of the door unit.

Abstract: Disclosed herein is a door hinge structure for a refrigerator.

Abstract: A microwave oven includes a door. The door includes a door unit for selectively opening/closing a cooking chamber and a control unit, for controlling an operation of the microwave oven, is arranged at a predetermined part of the door unit.