Abstract: A digital noise coupling circuit includes: an analog-to-digital converter (ADC) configured to convert a quantization error, generated in a process of converting a first analog signal into a first digital signal, into a first digital error signal; a delay cell comprising delay elements configured to delay a transmission of the first digital error signal based on a clock signal; and a digital-to-analog (DA) conversion circuit configured to perform, in an analog domain, noise shaping on the first digital error signal that is delayed and transmitted from the delay cell.

Abstract: A continuous time op-amp includes a differential op-amp configured to produce, and output through output lines, output signals amplified based on a difference between input signals inputted to the differential op-amp, and a common mode feedback (CMFB) circuit configured to feed a common mode voltage back to the op-amp through a feedback line in continuous time through a capacitive coupled path, wherein the CMFB circuit includes: feedback capacitors connected between the output lines and the feedback line; switched capacitors charged based on a common mode reference voltage; and switching elements configured to control a connection between the feedback capacitors and the switched capacitors.

Abstract: An amplification apparatus includes an amplifier having an inverting terminal, and a non-inverting terminal connected to a reset voltage node, a first capacitor connected to the inverting terminal, an input voltage being applied to the first capacitor, a second capacitor connected to the inverting terminal and an output terminal of the amplifier, and a duty-cycled resistor, connected in parallel to the second capacitor, including a first resistor. The duty-cycled resistor is configured to connect the first resistor and the inverting terminal and to disconnect the first resistor and the reset voltage node during a first time interval included in a period to complete an on-and-off cycle of the duty-cycled resistor, and disconnect the first resistor and the inverting terminal and to connect the first resistor and the reset voltage node during a second time interval included in the period.

Abstract: An analog-to-digital converter includes: a sample/hold circuit, which samples an analog signal, and outputs a first voltage; a digital-to-analog conversion circuit, which converts a digital signal to output a second voltage; an amplifier, which amplifies the first voltage and the second voltage; a noise shaping filter, which integrates a residual voltage corresponding to a difference between the amplified first voltage and the amplified second voltage, and generates a first integration voltage and a second integration voltage; a comparator, which compares a sum of the amplified first voltage, the first integration voltage, and the second integration voltage with the amplified second voltage; and a SAR logic, which outputs the digital signal according to a comparison result of the comparator, and controls the digital-to-analog conversion circuit.

Abstract: Methods of sensor readout and calibration and circuits for performing the methods are disclosed. In some embodiments, the methods include driving an active sensor at a voltage. In some embodiments, the methods include use of a calibration sensor, and the circuits include the calibration sensor. In some embodiments, the methods include use of a calibration current source and circuits include the calibration current source. In some embodiments, a sensor circuit includes a Sigma-Delta ADC. In some embodiments, a column of sensors is readout using first and second readout circuits during a same row time.

Abstract: Methods of sensor readout and calibration and circuits for performing the methods are disclosed. In some embodiments, the methods include driving an active sensor at a voltage. In some embodiments, the methods include use of a calibration sensor, and the circuits include the calibration sensor. In some embodiments, the methods include use of a calibration current source and circuits include the calibration current source. In some embodiments, a sensor circuit includes a Sigma-Delta ADC. In some embodiments, a column of sensors is readout using first and second readout circuits during a same row time.

Abstract: An amplification apparatus includes an amplifier having an inverting terminal, and a non-inverting terminal connected to a reset voltage node, a first capacitor connected to the inverting terminal, an input voltage being applied to the first capacitor, a second capacitor connected to the inverting terminal and an output terminal of the amplifier, and a duty-cycled resistor, connected in parallel to the second capacitor, including a first resistor. The duty-cycled resistor is configured to connect the first resistor and the inverting terminal and to disconnect the first resistor and the reset voltage node during a first time interval included in a period to complete an on-and-off cycle of the duty-cycled resistor, and disconnect the first resistor and the inverting terminal and to connect the first resistor and the reset voltage node during a second time interval included in the period.

Abstract: Methods of sensor readout and calibration and circuits for performing the methods are disclosed. In some embodiments, the methods include driving an active sensor at a voltage. In some embodiments, the methods include use of a calibration sensor, and the circuits include the calibration sensor. In some embodiments, the methods include use of a calibration current source and circuits include the calibration current source. In some embodiments, a sensor circuit includes a Sigma-Delta ADC. In some embodiments, a column of sensors is readout using first and second readout circuits during a same row time.

Abstract: An analog-to-digital converter includes an input buffer connected to an input terminal receiving an input signal through a first sampling switch, a comparator connected to the input buffer, a sampling capacitor connected between the input buffer and the comparator, and connected to a second sampling switch, a digital-to-analog converter connected to the comparator, and a controller, connected between the comparator and the digital-to-analog converter, configured to output a signal to the digital-to-analog converter based on the comparator.

Abstract: An electronic circuit includes a first converting circuit, an amplifying circuit, and a second converting circuit. The first converting circuit outputs a first residual voltage associated with converting an analog signal into a first digital signal and a second residual voltage generated based on the first residual voltage. The amplifying circuit generates a third residual voltage by amplifying the first residual voltage through an amplifying path during a first time duration and generates a fourth residual voltage by amplifying the second residual voltage through the amplifying path during a second time duration after the first time duration. The second converting circuit generates a second digital signal associated with the analog signal by performing an interpolation operation based on the third residual voltage and the fourth residual voltage.

Abstract: An electronic circuit includes an analog to digital converter (ADC) and a noise coupling filter. The ADC generates a digital output signal based on a first analog signal and a second analog signal. The noise coupling filter generates the second analog signal to be fed back for an input to the ADC, based on a first quantization error signal associated with converting the first analog signal to the digital output signal. The noise coupling filter performs noise shaping on a digital error signal derived from the quantization error signal and generates the second analog signal from a result of the noise shaping, using a clock in the digital domain.

Abstract: An electronic circuit includes a first converting circuit, an amplifying circuit, and a second converting circuit. The first converting circuit outputs a first residual voltage associated with converting an analog signal into a first digital signal and a second residual voltage generated based on the first residual voltage. The amplifying circuit generates a third residual voltage by amplifying the first residual voltage through an amplifying path during a first time duration and generates a fourth residual voltage by amplifying the second residual voltage through the amplifying path during a second time duration after the first time duration. The second converting circuit generates a second digital signal associated with the analog signal by performing an interpolation operation based on the third residual voltage and the fourth residual voltage.

Abstract: An analog-to-digital converter includes an input buffer connected to an input terminal receiving an input signal through a first sampling switch, a comparator connected to the input buffer, a sampling capacitor connected between the input buffer and the comparator, and connected to a second sampling switch, a digital-to-analog converter connected to the comparator, and a controller, connected between the comparator and the digital-to-analog converter, configured to output a signal to the digital-to-analog converter based on the comparator.

Abstract: An analog-to-digital converter (ADC) is provided. The ADC may include an input terminal configured to receive input signals, a digital-to-analog converter (DAC), a first switch configured to control a connection between the DAC and the input terminal, a comparator, a second switch configured to control a connection between the DAC and the comparator, and a controller configured to control the first switch, the second switch, the DAC and the comparator.

Abstract: An electronic circuit includes an analog to digital converter (ADC) and a noise coupling filter. The ADC generates a digital output signal based on a first analog signal and a second analog signal. The noise coupling filter generates the second analog signal to be fed back for an input to the ADC, based on a first quantization error signal associated with converting the first analog signal to the digital output signal. The noise coupling filter performs noise shaping on a digital error signal derived from the quantization error signal and generates the second analog signal from a result of the noise shaping, using a clock in the digital domain.

Abstract: An electronic circuit includes a reference ADC, a delay circuit, and a main ADC. The reference ADC converts an input signal to an upper bit string of output data, in response to a reference clock. The delay circuit delays a source clock by a delay time to output a main clock. The main ADC converts the input signal to a lower bit string of the output data, in response to the main clock. When a value of the most significant bit included in the lower bit string is identical to a value of the bit which is adjacent to the most significant bit and lower than the most significant bit, the delay time is adjusted based on a direction in which a level of the input signal is changed and the value of the most significant bit of the lower bit string.

Abstract: An analog-to-digital converter (ADC) is provided. The ADC comprises an input terminal configured to receive input signals, a digital-to-analog converter (DAC), a first switch configured to control a connection between the DAC and the input terminal, a comparator, a second switch configured to control a connection between the DAC and the comparator, and a controller configured to control the first switch, the second switch, the DAC and the comparator.

Abstract: The exemplary embodiments of the present disclosure relate to a phase adjustment apparatus, and its operation method, provided with a phase detector, phase controller and phase calibrator for reducing complexity of a circuit and enabling execution of a phase adjustment operation in the background.

Abstract: The exemplary embodiments of the present disclosure relate to a phase adjustment apparatus, and its operation method, provided with a phase detector, phase controller and phase calibrator for reducing complexity of a circuit and enabling execution of a phase adjustment operation in the background.

Abstract: An electronic circuit includes a reference ADC, a delay circuit, and a main ADC. The reference ADC converts an input signal to an upper bit string of output data, in response to a reference clock. The delay circuit delays a source clock by a delay time to output a main clock. The main ADC converts the input signal to a lower bit string of the output data, in response to the main clock. When a value of the most significant bit included in the lower bit string is identical to a value of the bit which is adjacent to the most significant bit and lower than the most significant bit, the delay time is adjusted based on a direction in which a level of the input signal is changed and the value of the most significant bit of the lower bit string.