Abstract: An electronic circuit includes a reference ADC and a plurality of sub-ADCs. The reference ADC converts an input signal to reference data in response to a reference clock. The plurality of sub-ADCs may respectively convert the input signal to a plurality of output data, in response respectively to the plurality of conversion clocks providing different timings. Based on a difference between the reference data and each of the plurality of output data and output data corresponding to the difference among the plurality of output data, a timing of a conversion clock associated with the output data corresponding to the difference among the plurality of conversion clocks is adjusted.

Abstract: A frequency divider is provided. Some embodiments of the present disclosure provide a CMOS logic-based high speed differential divider that is capable of acquiring a desired output swing voltage even at low supply voltages and is robust to clock skew and clock feedthrough, featuring low power consumption.

Abstract: A multi-level memory device may include a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell current flowing through a memory cell with a predetermined reference current, a current/voltage conversion circuit configured to convert a copied cell current obtained by copying the cell current into a cell voltage, a charging time determination circuit configured to determine a charging time during which the copied cell current is converted into the cell voltage and output a charging end signal, and a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs according to the cell voltage and the charging end signal.

Abstract: A multi-level memory device may include a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell current flowing through a memory cell with a predetermined reference current, a current/voltage conversion circuit configured to convert a copied cell current obtained by copying the cell current into a cell voltage, a charging time determination circuit configured to determine a charging time during which the copied cell current is converted into the cell voltage and output a charging end signal, and a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs according to the cell voltage and the charging end signal.

Abstract: A multi-level memory apparatus includes two or more current paths configured to pass currents having different levels, a memory cell selectively coupled to the two or more current paths, and a cell current copy unit configured to copy a cell current flowing through the memory cell.

Abstract: This disclosure provides circuits and methods for reducing sub-threshold leakage currents discharging floating nodes. In one aspect, feedback from a floating node is provided to a feedback transistor configured to bias other nodes such that leakage through turned-off transistors is reduced. Additionally, leakage contributing to static power consumption may also be reduced.

Abstract: A multi-level memory apparatus includes two or more current paths configured to pass currents having different levels, a memory cell selectively coupled to the two or more current paths, and a cell current copy unit configured to copy a cell current flowing through the memory cell.

Abstract: An analog-to-digital converter includes: a first latch row corresponding to a first stage; a second latch row corresponding to a second stage; and a digital processor for encoding output signals of the second latch row and generating a digital signal. The first latch row includes a plurality of first latches that receive an analog input signal and reference voltages and operate in synchronization with a first clock signal, and the second latch row includes: a plurality of second latches that receive outputs signals of the plurality of first latches and operate in synchronization with a second clock signal delayed from the first reference clock; and a plurality of third latches that receive output signals of two neighboring latches of the plurality of first latches and operate in synchronization with the second clock signal by means of an interpolation technique.

Abstract: A capacitor is provided. The capacitor includes first and second electrode layers facing each other, a first conductive pattern disposed between the first and second electrode layers, the first conductive pattern forming a closed loop in plan view, a second conductive pattern disposed within an inner space surrounded by the closed loop of the first conductive pattern, the second conductive pattern being spaced from the first conductive pattern, and a first contact plug passing through the second conductive pattern to contact the first and second electrode layers.

Abstract: A phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO) with a variable gain is provided. A phase frequency detector (PFD) detects a phase difference between a reference signal and a PLL feedback signal. A charge pump and a loop filter sequentially process an output signal of the PFD. A VCO has different gains according to a mode transition. A control voltage applied to the VCO is selected from an output signal of the loop filter and an additional control signal according to the mode transition.

Abstract: An analog-to-digital converter includes: a first latch row corresponding to a first stage; a second latch row corresponding to a second stage; and a digital processor for encoding output signals of the second latch row and generating a digital signal. The first latch row includes a plurality of first latches that receive an analog input signal and reference voltages and operate in synchronization with a first clock signal, and the second latch row includes: a plurality of second latches that receive outputs signals of the plurality of first latches and operate in synchronization with a second clock signal delayed from the first reference clock; and a plurality of third latches that receive output signals of two neighboring latches of the plurality of first latches and operate in synchronization with the second clock signal by means of an interpolation technique.

Abstract: A digital feedforward sigma-delta modulator in an analog-to-digital converter and its modulation method are disclosed. The modulator changes a feedforward path from an analog domain to a digital domain and processes it. The modulator integrates an analog input by using a plurality of integrators, weights them, quantizes them by using a plurality of quantizers in a digital domain to output digital signals, and then adds up the thusly outputted digital signals by using a digital adder. In case of a continuous time digital feedforward sigma-delta modulator (SDM), a digital signal outputted from the digital adder is weighted and then immediately inputted to the digital adder in the digital domain so as to be subtracted, allowing for digital feedforwarding. Because the feedforward signal is processed in the digital domain, the area occupied by an analog circuit and power consumption can be reduced.

Abstract: A digital feedforward sigma-delta modulator in an analog-to-digital converter and its modulation method are disclosed. The modulator changes a feedforward path from an analog domain to a digital domain and processes it. The modulator integrates an analog input by using a plurality of integrators, weights them, quantizes them by using a plurality of quantizers in a digital domain to output digital signals, and then adds up the thusly outputted digital signals by using a digital adder. In case of a continuous time digital feedforward sigma-delta modulator (SDM), a digital signal outputted from the digital adder is weighted and then immediately inputted to the digital adder in the digital domain so as to be subtracted, allowing for digital feedforwarding. Because the feedforward signal is processed in the digital domain, the area occupied by an analog circuit and power consumption can be reduced.

Abstract: An apparatus for digital error correction in a successive approximation (SAR) analog to digital converter (ADC) includes a binary weighted digital to analog converter (DAC) which can be virtually divided into multiple sub-DACs for redundancy insertion; and a comparator configured to compare the analog input with a DAC level corresponding to digital. The apparatus further includes a register and control logic unit configured to control a switching operation for DAC and to add output codes obtained from sub-DACs to output the added code as a final A/D converted code.

Abstract: A phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO) with a variable gain is provided. A phase frequency detector (PFD) detects a phase difference between a reference signal and a PLL feedback signal. A charge pump and a loop filter sequentially process an output signal of the PFD. A VCO has different gains according to a mode transition. A control voltage applied to the VCO is selected from an output signal of the loop filter and an additional control signal according to the mode transition.

Abstract: An apparatus for digital error correction in a successive approximation (SAR) analog to digital converter (ADC) includes a binary weighted digital to analog converter (DAC) which can be virtually divided into multiple sub-DACs for redundancy insertion; and a comparator configured to compare the analog input with a DAC level corresponding to digital. The apparatus further includes a register and control logic unit configured to control a switching operation for DAC and to add output codes obtained from sub-DACs to output the added code as a final A/D converted code.

Abstract: An electronic circuit includes a digital-to-analog converter (DAC), and an active integrator. The DAC converts a digital output of the electronic circuit to an analog signal and feeds back the analog signal. The active integrator includes an operational amplifier having a first input terminal that receives a summed signal of an input signal and the fed back analog signal, and a second input terminal that receives a reference voltage. The DAC includes a coupling capacitor, first switches, at least one current source, second switches, and a third switch.

Abstract: A pipelined analog-to-digital converter (ADC) has a multistage structure, and the pipelined ADC includes a plurality of stages that form the multistage structure. Each of the stages includes a sample-and-hold (S/H) circuit, a flash ADC, and a digital-to-analog converter (DAC). The S/H circuit converts an analog input signal to a digital signal. The flash ADC detects a digital bit corresponding to the analog input signal. The DAC converts the digital signal to an analog signal, and amplifies a residue signal, which is a difference between the input analog signal and the converted analog signal, that is provided as an analog input signal of the next stage.

Abstract: An electronic circuit includes a digital-to-analog converter (DAC), and an active integrator. The DAC converts a digital output of the electronic circuit to an analog signal and feeds back the analog signal. The active integrator includes an operational amplifier having a first input terminal that receives a summed signal of an input signal and the fed back analog signal, and a second input terminal that receives a reference voltage. The DAC includes a coupling capacitor, first switches, at least one current source, second switches, and a third switch.

Abstract: A pipelined analog-to-digital converter (ADC) has a multistage structure, and the pipelined ADC includes a plurality of stages that form the multistage structure. Each of the stages includes a sample-and-hold (S/H) circuit, a flash ADC, and a digital-to-analog converter (DAC). The S/H circuit converts an analog input signal to a digital signal. The flash ADC detects a digital bit corresponding to the analog input signal. The DAC converts the digital signal to an analog signal, and amplifies a residue signal, which is a difference between the input analog signal and the converted analog signal, that is provided as an analog input signal of the next stage.