Abstract: A display device includes: a substrate; a transistor on the substrate; an interlayer insulating layer on the transistor; a first electrode disposed on the interlayer insulating layer and connected to the transistor through a contact hole in the interlayer insulating layer; a pixel defining layer disposed on the interlayer insulating layer and the first electrode; a sacrificial layer disposed in a groove of the interlayer insulating layer; a gap fill layer disposed on the sacrificial layer, between a first sub-pixel defining layer and a second sub-pixel defining layer included in the pixel defining layer; a light emitting stack on the first electrode and the pixel defining layer; and a first trench formed between the first sub-pixel defining layer and the gap fill layer, between an inner wall of the groove and the gap fill layer, and between the inner wall of the groove and the sacrificial layer.

Abstract: A display device includes a substrate including a display area and a non-display area, a plurality of pixels disposed in the display area, a common voltage supply wiring overlapping the non-display area and disposed on the substrate, a driving voltage supply wiring overlapping the non-display area and disposed on the substrate, and a data voltage supply wiring overlapping the non-display area and electrically connected to the plurality of pixels, where at least one of the common voltage supply wiring and the driving voltage supply wiring includes a chamfered area, the data voltage supply wiring includes a first data voltage supply wiring, a second data voltage supply wiring, and a third data voltage supply wiring, and the first to third data voltage supply wirings are disposed in different layers.

Abstract: A display device may include a first pixel column disposed on a substrate, a second pixel column adjacent to the first pixel column, a third pixel column adjacent to the second pixel column, and a first wiring, a second wiring, and a third wiring respectively and electrically connected to the first pixel column, the second pixel column, and the third pixel column. Each of the first wiring, the second wiring, and the third wiring may include a first line, a second line electrically connected to the first line, the first line and the second line being disposed on different layers, and a third line electrically connected to the second line, the first line, the second line, and the third line being disposed on different layers.

Abstract: A display device includes a substrate including a display area and a non-display area, a plurality of pixels disposed in the display area, a common voltage supply wiring overlapping the non-display area and disposed on the substrate, a driving voltage supply wiring overlapping the non-display area and disposed on the substrate, and a data voltage supply wiring overlapping the non-display area and electrically connected to the plurality of pixels, where at least one of the common voltage supply wiring and the driving voltage supply wiring includes a chamfered area, the data voltage supply wiring includes a first data voltage supply wiring, a second data voltage supply wiring, and a third data voltage supply wiring, and the first to third data voltage supply wirings are disposed in different layers.

Abstract: A display device may include a first pixel column disposed on a substrate, a second pixel column adjacent to the first pixel column, a third pixel column adjacent to the second pixel column, and a first wiring, a second wiring, and a third wiring respectively and electrically connected to the first pixel column, the second pixel column, and the third pixel column. Each of the first wiring, the second wiring, and the third wiring may include a first line, a second line electrically connected to the first line, the first line and the second line being disposed on different layers, and a third line electrically connected to the second line, the first line, the second line, and the third line being disposed on different layers.

Abstract: Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.

Abstract: Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.

Abstract: Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.

Abstract: Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.

Abstract: Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.

Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing thereof are disclosed. In one aspect, the display includes a scan line formed over a substrate and configured to provide a scan signal. An initialization voltage line has substantially the same pattern as the scan line and is insulated from the scan line. A data line crosses the scan line and is configured to provide a data voltage. A switching transistor is electrically connected to the scan line and the data line, and a driving transistor is electrically connected to the switching transistor and includes a driving gate electrode. A storage capacitor includes a first storage electrode and a second storage electrode overlapping the first storage electrode, wherein the first storage electrode and the driving gate electrode are integrally formed.

Abstract: An organic light emitting diode display includes: first gate wires provided on a substrate with a first insulation layer therebetween and extended in a first direction; second gate wires provided on a second insulation layer above the first insulation layer and extended in the first direction; data wires provided on a third insulation layer above the second insulation layer and extended in a second direction crossing the first direction; a pixel circuit connected to the first gate wires, the second gate wires, and the data wires; and an organic light emitting diode connected to the pixel circuit.

Abstract: Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.

Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing thereof are disclosed. In one aspect, the display includes a scan line formed over a substrate and configured to provide a scan signal. An initialization voltage line has substantially the same pattern as the scan line and is insulated from the scan line. A data line crosses the scan line and is configured to provide a data voltage. A switching transistor is electrically connected to the scan line and the data line, and a driving transistor is electrically connected to the switching transistor and includes a driving gate electrode. A storage capacitor includes a first storage electrode and a second storage electrode overlapping the first storage electrode, wherein the first storage electrode and the driving gate electrode are integrally formed.

Abstract: A semiconductor device includes a semiconductor layer over a substrate. The semiconductor layer changes direction at least twice and has at least two different widths in the same plane. The length of a current path through the semiconductor layer is greater than a shortest path through the semiconductor layer in the same plane.

Abstract: A display device includes: an insulating substrate comprising a first region and a second region; a thin-film transistor (TFT) formed on the first region comprising a gate electrode, a source electrode, and a drain electrode; and a storage capacitor formed on the second region, wherein the storage capacitor comprises a first electrode, a second electrode and a first interlayer insulating film, where the first and second electrodes face each other and are made of a transparent conductive material, wherein the interlayer insulating film is interposed between the first electrode and the second electrode, and wherein the first electrode is formed on the entire surface of the first substrate as one body and receives a common voltage, and the second electrode is electrically connected to the drain electrode.

Abstract: A liquid crystal display device is disclosed.

Abstract: A display substrate includes a signal line, a test switch, a test pad, and a first electrostatic dispersion line. The signal line is formed in the display area of a base substrate. The test switch is formed in a peripheral area of the base substrate surrounding the display area. The test switch applies a test signal to the signal line. The test pad is electrically connected to the test switch and receives the test signal. The first electrostatic dispersion line is extended from the test pad to an end of the base substrate.

Abstract: A liquid crystal display device is disclosed. The device includes: a first substrate, a thin film transistor formed in a first, non-transmissive region on the first substrate, including a gate electrode, a source electrode and a drain electrode, and a storage capacitor formed in a second, transmissive region on the first substrate, where a first electrode and a second electrode of the storage capacitor are made of a transparent conductive material.

Abstract: A flat panel display device having increased capacitance and a method of manufacturing the flat panel display device are provided. A flat panel display device includes: a plurality of pixel areas, each located at a crossing region of a gate line, a data line, and a common voltage line; a thin film transistor (TFT) located at a region where the gate line and the data line cross each other, the TFT including a gate electrode, a source electrode, and a drain electrode; and a storage capacitor located at a region where the common voltage line and the drain electrode cross each other, the storage capacitor including first, second, and a third storage electrodes.