Patents by Inventor Seung-Mok Shin

Seung-Mok Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11962001
    Abstract: Disclosed is a positive electrode material for a lithium secondary battery. The positive electrode material includes a positive electrode active material formed of Li—[Mn—Ti]-M-O-based material including a transition metal (M) to enable reversible intercalation and deintercalation of lithium and molybdenum oxide. The positive electrode active material is coated with the molybdenum oxide to form a coating layer on a surface thereof.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: April 16, 2024
    Assignees: Hyundai Motor Company, Kia Corporation, Industry Academy Cooperation Foundation of Sejong University
    Inventors: Seung Min Oh, Jun Ki Rhee, Yoon Sung Lee, Ji Eun Lee, Sung Ho Ban, Ko Eun Kim, Woo Young Jin, Sang Mok Park, Sang Hun Lee, Seung Taek Myung, Hee Jae Kim, Min Young Shin
  • Patent number: 9343475
    Abstract: In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: May 17, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Tae Jang, Sang-Hoon Lee, Ji-Youn Seo, Hyun-Yong Go, Koong-Hyun Nam, Ju-Wan Kim, Seung-Mok Shin, Myoung-Bum Lee, Ji-Woon Im, Tae-Jong Han
  • Publication number: 20150200203
    Abstract: In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 16, 2015
    Inventors: Kyung-Tae Jang, Sang-Hoon Lee, Ji-Youn Seo, Hyun-Yong Go, Koong-Hyun Nam, Ju-Wan Kim, Seung-Mok Shin, Myoung-Bum Lee, Ji-Woon Im, Tae-Jong Han
  • Patent number: 8976328
    Abstract: A liquid crystal display device includes a first substrate having a thin film transistor (TFT) in each pixel region, a first inorganic protective film on the first substrate including the TFT, color filters on the first inorganic protective film in each pixel region excluding the TFT, a common electrode on the color filters, a second protective film over the entire first inorganic protective film including the common electrode, a pixel electrode on the second inorganic protective film with the pixel electrode connected to a drain electrode of the TFT exposed by selective removal of the first and second inorganic protective films, the pixel electrode forming a fringe field with the common electrode such that the second inorganic protective film is interposed between the pixel electrode and the common electrode, and a column spacer on the second inorganic protective film with the column spacer covering the TFT.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 10, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Jin-Tae Kim, Myung-Woo Nam, Seung-Mok Shin, Soo-Jeong Choi
  • Patent number: 8643084
    Abstract: A vertical non-volatile memory device includes a semiconductor pattern disposed on a substrate; and a plurality of transistors of first through n-th layers that are stacked on a side of the semiconductor pattern at predetermined distances from each other, wherein the transistors are spaced apart and insulated from one another at the predetermined distances via air gap, where n is a natural number equal to or greater than 2.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Mok Shin, Kyung-Tae Jang, Chang-Won Lee
  • Patent number: 8588235
    Abstract: A system and method for providing a multicast/broadcast service (MBS) using a Wireless Broadband Internet/World Interoperability for Microwave Access (WiBro/WiMAX) network are provided, which include an MBS control unit for generating a beginning and an end of an MBS bearer session, a quality of service (QoS) control unit for requesting an allocation and release of a QoS, an access control router (ACR) for allocating a multicast service flow identifier (SFID) with respect to the MBS bearer session in order to provide an MBS user terminal with MBS bearer traffic which is received from an MBS content source, and for releasing the allocated multicast SFID when the release of the QoS is requested, and a radio access station (RAS) for allocating a multicast connection identifier (CID) corresponding to the allocated multicast SFID according to whether an MBS user requests the MBS bearer traffic, and controlling a radio resource with the MBS user terminal.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: November 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mi-Sun Do, Seung Mok Shin, Taori Rakesh
  • Patent number: 8547978
    Abstract: A system and method for providing Multicast/Broadcast Service (MBS) service to a mobile terminal in an MBS service provisioning system in a Wide Area Network (WAN) network are provided. An authentication server sends a message for requesting resource reservation, in which a Quality-of-Service (QoS) policy is included, when a registration procedure of the mobile terminal is performed. A base station stores the message sent from the authentication server, forwards the message to the mobile terminal, and sets up a channel to the mobile terminal upon receiving from the mobile terminal a request for channel setup based on the QoS policy.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mi-Sun Do, Seung-Mok Shin, Jang-Woo Son, Jong-Ho Bang
  • Publication number: 20120068242
    Abstract: A semiconductor device includes horizontal patterns on a substrate and the horizontal patterns have at least one opening therein, a pad pattern in an upper region of the opening, an insulating gap fill structure in the opening, the insulating gap fill structure is between the pad pattern and the substrate, and the insulating gap fill structure includes a first gap fill pattern and a second gap fill pattern. The first gap fill pattern includes a first oxide and the second gap fill pattern includes a second oxide, and the second oxide has a different etching selectivity from that of the first oxide. The device further includes a semiconductor pattern that is between a sidewall of the gap fill structure and sidewalls of the horizontal patterns and between a sidewall of the pad pattern and the sidewalls of the horizontal patterns.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 22, 2012
    Inventors: Seung-Mok SHIN, Ju-Eun Kim
  • Publication number: 20120012920
    Abstract: A vertical non-volatile memory device includes a semiconductor pattern disposed on a substrate; and a plurality of transistors of first through n-th layers that are stacked on a side of the semiconductor pattern at predetermined distances from each other, wherein the transistors are spaced apart and insulated from one another at the predetermined distances via air gap, where n is a natural number equal to or greater than 2.
    Type: Application
    Filed: July 13, 2011
    Publication date: January 19, 2012
    Inventors: Seung-Mok SHIN, Kyung-Tae Jang, Chang-Won Lee
  • Patent number: 7592227
    Abstract: Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: September 22, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sun Lee, Jai-Dong Lee, Bong-Hyun Kim, Man-Sug Kang, Jung-Hwan Kim, Hyun-Jin Shin, Won-Seok Yoo, Seung-Mok Shin
  • Publication number: 20080123543
    Abstract: A system and method for providing Multicast/Broadcast Service (MBS) service to a mobile terminal in an MBS service provisioning system in a Wide Area Network (WAN) network are provided. An authentication server sends a message for requesting resource reservation, in which a Quality-of-Service (QoS) policy is included, when a registration procedure of the mobile terminal is performed. A base station stores the message sent from the authentication server, forwards the message to the mobile terminal, and sets up a channel to the mobile terminal upon receiving from the mobile terminal a request for channel setup based on the QoS policy.
    Type: Application
    Filed: July 2, 2007
    Publication date: May 29, 2008
    Inventors: Mi-Sun Do, Seung-Mok Shin, Jang-Woo Son, Jong-Ho Bang
  • Publication number: 20080101376
    Abstract: A system and method for providing a multicast/broadcast service (MBS) using a Wireless Broadband Internet/World Interoperability for Microwave Access (WiBro/WiMAX) network are provided, which include an MBS control unit for generating a beginning and an end of an MBS bearer session, a quality of service (QoS) control unit for requesting an allocation and release of a QoS, an access control router (ACR) for allocating a multicast service flow identifier (SFID) with respect to the MBS bearer session in order to provide an MBS user terminal with MBS bearer traffic which is received from an MBS content source, and for releasing the allocated multicast SFID when the release of the QoS is requested, and a radio access station (RAS) for allocating a multicast connection identifier (CID) corresponding to the allocated multicast SFID according to whether an MBS user requests the MBS bearer traffic, and controlling a radio resource with the MBS user terminal.
    Type: Application
    Filed: June 21, 2007
    Publication date: May 1, 2008
    Inventors: Mi-Sun Do, Seung Mok Shin, Taori Rakesh
  • Patent number: 7342286
    Abstract: According to example embodiments of the present invention, there are provided an electrical node of a transistor and a method of forming the same, which may reduce or minimize current leakage between the electrical node and a semiconductor substrate when a buried contact hole exposing at least the side of an active region is arranged on the semiconductor substrate. Two gate patterns may be formed on the active region of the semiconductor substrate. Conductive layer patterns may be formed in the gate patterns and in the semiconductor substrate between the gate patterns. A buried interlayer insulating layer may be formed on the semiconductor substrate to cover the gate patterns. A buried contact hole which passes through the buried interlayer insulating layer and exposes the conductive layer pattern of the semiconductor substrate may be formed. The buried contact hole may be formed to expose at least the side of the active region.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: March 11, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Mok Shin, Jin-Hong Kim, Soo-Woong Lee
  • Publication number: 20070010068
    Abstract: Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode.
    Type: Application
    Filed: July 7, 2006
    Publication date: January 11, 2007
    Inventors: Yong-Sun Lee, Jai-Dong Lee, Bong-Hyun Kim, Man-Sug Kang, Jung-Hwan Kim, Hyun-Jin Shin, Won-Seok Yoo, Seung-Mok Shin
  • Patent number: 7101803
    Abstract: In accordance with a method of trench isolation, a first oxide layer is formed on a semiconductor substrate. A first conductive layer and a nitride layer are successively formed on the first oxide layer. The nitride layer, the first conductive layer and the first oxide layer are etched to form a nitride layer pattern, a first conductive layer pattern and an oxide layer pattern. A portion of the substrate adjacent to the first conductive layer pattern is etched to form a trench in the substrate. The trench is cured under dinitrogen monoxide (N2O) or nitrogen monoxide(NO) atmosphere. A second oxide layer is formed in the trench through an in-situ process.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: September 5, 2006
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Sang-Hoon Lee, Hun-Hyeoung Leam, Seung-Mok Shin, Woo-Sung Lee
  • Publication number: 20060138564
    Abstract: According to example embodiments of the present invention, there are provided an electrical node of a transistor and a method of forming the same, which may reduce or minimize current leakage between the electrical node and a semiconductor substrate when a buried contact hole exposing at least the side of an active region is arranged on the semiconductor substrate. Two gate patterns may be formed on the active region of the semiconductor substrate. Conductive layer patterns may be formed in the gate patterns and in the semiconductor substrate between the gate patterns. A buried interlayer insulating layer may be formed on the semiconductor substrate to cover the gate patterns. A buried contact hole which passes through the buried interlayer insulating layer and exposes the conductive layer pattern of the semiconductor substrate may be formed. The buried contact hole may be formed to expose at least the side of the active region.
    Type: Application
    Filed: December 29, 2005
    Publication date: June 29, 2006
    Inventors: Seung-Mok Shin, Jin-Hong Kim, Soo-Woong Lee
  • Patent number: 6881637
    Abstract: In a method for forming a gate electrode having an excellent sidewall profile, after a gate structure is formed on a substrate, a first oxide film is formed on a sidewall of the gate structure and on the substrate by re-oxidizing the gate structure and the substrate under an atmosphere including an oxygen gas and an inert gas. The gate structure has a gate oxide film pattern, a polysilicon film pattern and a metal silicide film pattern. A portion of the first oxide film formed on a sidewall of the polysilicon film pattern has a thickness substantially identical to that of a portion of the first oxide film formed on a sidewall of the metal silicide film pattern. A failure of a semiconductor device having the gate electrode can be minimized because the gate electrode has an improved sidewall profile.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: April 19, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Jong Han, Yong-Woo Hyung, Seung-Mok Shin, Kong-Soo Lee, Eun-Jung Yun
  • Patent number: 6828254
    Abstract: A plasma enhanced chemical vapor deposition apparatus and a method of forming a nitride layer using the same, wherein the plasma enhanced CVD apparatus includes a process chamber including an upper chamber with a dome shape, a lower chamber, and an insulator therebetween, a gas distributing ring, a susceptor for supporting a wafer and heating the process chamber, a plasma compensation ring surrounding the susceptor, a vacuum pump and an electric power source connected to the process chamber. The gas distributing ring has a plurality of upwardly inclined nozzles, allowing upward distribution of reactive gases. The method of forming a nitride layer includes forming a protective film on inner walls of a process chamber, the protective film having at least two layers of differeing dielectric constant, and sequentially supplying reactive gases to the process chamber. A nitride layer formed thereby has low hydrogen content, good density and oxidation resistance.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: December 7, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Jong Han, Kyoung-Seok Kim, Byung-Ho Ahn, Seung Mok Shin, Hwa-Sik Kim, Hong-Bae Park
  • Patent number: 6815370
    Abstract: A plasma enhanced chemical vapor deposition apparatus and a method of forming a nitride layer using the same, wherein the plasma enhanced CVD apparatus includes a process chamber including an upper chamber with a dome shape, a lower chamber, and an insulator therebetween, a gas distributing ring, a susceptor for supporting a wafer and heating the process chamber, a plasma compensation ring surrounding the susceptor, a vacuum pump and an electric power source connected to the process chamber. The gas distributing ring has a plurality of upwardly inclined nozzles, allowing upward distribution of reactive gases. The method of forming a nitride layer includes forming a protective film on inner walls of a process chamber, the protective film having at least two layers of differeing dielectric constant, and sequentially supplying reactive gases to the process chamber. A nitride layer formed thereby has low hydrogen content, good density and oxidation resistance.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: November 9, 2004
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Jae-Jong Han, Kyoung-Seok Kim, Byung-Ho Ahn, Seung Mok Shin, Hwa-Sik Kim, Hong-Bae Park
  • Publication number: 20040182815
    Abstract: In accordance with a method of trench isolation, a first oxide layer is formed on a semiconductor substrate. A first conductive layer and a nitride layer are successively formed on the first oxide layer. The nitride layer, the first conductive layer and the first oxide layer are etched to form a nitride layer pattern, a first conductive layer pattern and an oxide layer pattern. A portion of the substrate adjacent to the first conductive layer pattern is etched to form a trench in the substrate. The trench is cured under dinitrogen monoxide (N2O) or nitrogen monoxide(NO) atmosphere. A second oxide layer is formed in the trench through an in-situ process.
    Type: Application
    Filed: February 23, 2004
    Publication date: September 23, 2004
    Applicant: Samsung Electronic Co. Ltd.
    Inventors: Sang-Hoon Lee, Hun-Hyeoung Leam, Seung-Mok Shin, Woo-Sung Lee