Abstract: The present invention relates to a novel use of NCKAP1 gene in neurodegenerative diseases. More specifically, the present invention relates to a marker composition for predicting the prognosis of a neurodegenerative disease, comprising a NCKAP1 protein or a gene encoding same, a composition and a kit for predicting the prognosis of a neurodegenerative disease, which comprises a formulation for measuring the level of the protein or an mRNA of the gene encoding same, and a pharmaceutical composition for preventing or treating neurodegenerative disease, comprising the protein or the gene encoding same as an active ingredient.

Abstract: The present invention relates to a high voltage-type redox flow battery comprising: a plurality of modules (1001, 1002, 1003, . . , 100n) which are serially connected; and a battery management system (BMS) for monitoring a state-of-charge (SOC) of each of the plurality of modules (1001, 1002, 1003, ..

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Abstract: The present invention relates to a method for preparing a sulfide-based solid electrolyte, a sulfide-based solid electrolyte prepared by the method, and an all-solid-state lithium secondary battery including the sulfide-based solid electrolyte. The method of the present invention includes a) mixing Li2S with P2S5 to prepare a mixed powder, b) placing the mixed powder, an ether, and stirring balls in a container, sealing the container, followed by stirring to prepare a suspension, and c) stirring the suspension under high-temperature and high-pressure conditions to prepare sulfide-based solid particles.

Abstract: Provided is a method for preparing cell-derived vesicles, and more particularly, a method for preparing cell-derived vesicles using a cell extruder, and a syringe-type cell extruder for effectively preparing cell-derived vesicles. According to the present invention, by using the method for preparing the cell-derived vesicles and the cell extruder, it is possible to prepare cell-derived vesicles in a stable, economical, and mass-producible manner.

Abstract: The present disclosure provides methods for processing cell-derived vesicles in which the cell-derived vesicles are not purified, prior to contacting with a fluorescent staining dye or an antibody. By utilizing a centrifugal filter, excess staining dye or antibody can be readily removed prior to analysis of one or more characteristics of the cell-derived vesicles. The methods provide rapid and simple processing and analysis, while maintaining a high concentration of cell-derived vesicles.

Abstract: The present invention relates to cell-derived vesicles comprising target protein Prokineticin receptor 1 (PROKR1), and a therapeutic agent for muscle diseases comprising the same. When applied to myoblasts, the cell-derived vesicles comprising PROKR1 according to the present invention promote muscle differentiation and induce differentiation into myotubes, and can thus be used to prevent or treat muscle diseases and can be widely used in the pharmaceutical industry and the field of health functional foods.

Abstract: An electronic device includes an enable signal generation circuit configured to activate, when a write operation is performed, a termination enable signal earlier than a time point when a write latency elapses, by a duration amount of an entry offset period; and a data input and output circuit configured to receive, when the write operation is performed, data later than the time point when the write latency elapses, based on the termination enable signal, wherein the data input and output circuit receives the data after the write latency elapses by a duration amount of a first data reception delay period.

Abstract: The present invention relates to a salivary gland therapeutic agent using the effects of a cell-derived vesicle of enhancing the proliferation capacity of salivary gland cells, promoting an amylase activity, and enhancing transepithelial resistance. A pharmaceutical composition comprising the cell-derived vesicle according to the present invention has the effects of enhancing the proliferation capacity of salivary gland cells damaged by radiation, promoting amylase activity, increasing transepithelial resistance, enhancing the expression of Aquaporin 5, and increasing the amount of saliva secretion. Therefore, the pharmaceutical composition comprising the cell-derived vesicle of the present invention can be used for preventing and treating salivary gland diseases, and thus can be widely used in the pharmaceutical industry and health functional food field.

Abstract: An electronic device includes an enable signal generation circuit configured to activate, when a write operation is performed, a termination enable signal earlier than a time point when a write latency elapses, by a duration amount of an entry offset period; and a data input and output circuit configured to receive, when the write operation is performed, data later than the time point when the write latency elapses, based on the termination enable signal, wherein the data input and output circuit receives the data after the write latency elapses by a duration amount of a first data reception delay period.

Abstract: A semiconductor system includes a memory controller and a memory apparatus. The memory controller provides at least first to third command address signals. The memory apparatus performs a burst read operation based on the first and second command address signals, and terminates the burst read operation by receiving the third command address signal twice. The memory apparatus continuously initializes an internal circuit that is performing the burst read operation in a section the third command address signal is received twice.

Abstract: A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

Abstract: A semiconductor system includes a memory controller and a memory apparatus. The memory controller provides at least first to third command address signals. The memory apparatus performs a burst read operation based on the first and second command address signals, and terminates the burst read operation by receiving the third command address signal twice. The memory apparatus continuously initializes an internal circuit that is performing the burst read operation in a section the third command address signal is received twice.

Abstract: A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

Abstract: An electronic device may include: a column control circuit configured to generate a column control pulse and a mode register enable signal, each with a pulse that is generated based on logic levels of a chip selection signal and a command address; and a control circuit configured to generate a read control signal to perform a read operation and a mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal and configured to generate a mode register control signal to perform the mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal.

Abstract: A signal driver includes a first driver, a second driver, an on-timing control circuit, and an off-timing control circuit. The first driver is configured to generate a first driving pulse signal by inverting and driving an input pulse signal. The second driver is configured to generate a second driving pulse signal by inverting and driving the first driving pulse signal. The on-timing control circuit is configured to pull-up drive or pull-down drive the first driving pulse signal based on a first on-timing control signal, a second on-timing control signal, and the input pulse signal. The off-timing control circuit is configured to pull-up drive or pull-down drive the second driving pulse signal based on a first off-timing control signal, a second off-timing control signal, and the first driving pulse signal.

Abstract: A semiconductor device includes an internal clock generation circuit, a command generation circuit, and an address generation circuit. The internal clock generation circuit generates a command clock signal and an inverted command clock signal, wherein a cycle of the command clock signal and a cycle of the inverted command clock signal are determined by a mode. The command generation circuit generates a first command based on a first internal control signal and the command clock signal and generates a second command based on a second internal control signal and the inverted command clock signal. The address generation circuit generates a latch address based on the first internal control signal or a second internal control signal.

Abstract: A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

Abstract: A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

Abstract: A semiconductor device and command generation method, the semiconductor device includes a command recovery circuit configured to receive a command from a plurality of commands, to store a code signal which is generated by encoding the received command from the plurality of commands, depending on the received command, and generate a plurality of internal commands by decoding a command code signal which is generated from the code signal after shifting the received command depending on a shifting control signal; and a memory circuit configured to perform an internal operation depending on the plurality of internal commands.