Abstract: A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

Abstract: A method for forming damascene interconnect copper diffusion barrier layers includes implanting calcium into the sidewalls of the trenches and vias. The calcium implantation into dielectric layers, such as oxides, is used to prevent Cu diffusion into oxide, such as during an annealing process step. The improved barrier layers of the present invention help prevent delamination of the Cu from the dielectric.

Abstract: A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolyS1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.

Abstract: A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.

Abstract: A carbon nanotube memory cell for an integrated circuit wherein a chamber is constructed in a layer of a dielectric material such as silicon nitride down to a first electrical contact. This chamber is filled with polysilicon. A layer of a carbon nanotube mat or ribbon is formed over the silicon nitride layer and the chamber. A dielectric material, such as an oxide layer, is formed over the nanotube strips and patterned to form an upper chamber down to the ribbon layer to permit the ribbon to move into the upper chamber or into the lower chamber. The upper chamber is then filled with polysilicon. A silicon nitride layer is formed over the oxide layer and a contact opening is formed down to the ribbon and filled with tungsten that is then patterned to form metal lines. Any exposed silicon nitride is removed. A polysilicon layer is formed over the tungsten lines and anisotropically etched to remove polysilicon on the horizontal surfaces but leave polysilicon sidewall spacers.

Abstract: A metal layer formed on a semiconductor wafer is planarized by applying sequentially a deplating step, a plating step, and a relaxation step in a removal cycle. A series of cycles are performed sequentially in one embodiment to comprise a pass. The removal cycle is repeated in sequence until the pass is completed. The respective deplating and plating rates are adjusted so that the ratios of deplating rates to plating rates progressively decrease from an initial pass to a final pass. Organic additives are added to the electrolytic plating solution to control the plating portion of the cycle in a topography dependant fashion.

Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group IV metal.

Abstract: An integrated circuit device which includes a surface alloy layer, where the alloy layer forms a protective and adherent thin layer which improves electromigration performance. A method includes steps of forming one or more trench and/or via structures, depositing a thin TaN/Ta barrier layer stack and then a Copper seed layer, depositing and filling the via/trench with a thick Copper layer, removing the metal layers over in the field area, depositing, for example, a layer of Aluminum over the structure, annealing the devices in a protective atmosphere to allow Aluminum to react with Copper to form a thin Copper-Aluminum alloy, and removing the Aluminum metal layers over the field area, forming a thin layer of Al2O3, AlN or Al3C4 over the Copper-Aluminum for protection. During subsequent deposition of barrier and seed, the top surface layer of the Al2O3, AlN or Al3C4 is preferably removed to ensure the integrity of metal contact.

Abstract: A light emitting phosphor material for an alternating current thin-film electroluminescent device that includes the phosphor material sandwiched between a pair of dielectric layers. The phosphor material comprises a first layer having a thickness greater than 600 nanometers wherein the first phosphor material has a luminance output at 25 degrees C. and a decreased luminance output at 50 degrees C. greater than 20 percent of the luminance output at 25 degrees C. The phosphor material comprises a second phosphor layer overlaying the first phosphor layer having a thickness less than 400 nanometers wherein the decreased luminance output at 50 degrees C. is less than 20 percent with the second phosphor layer.

Abstract: A light emitting phosphor material for an alternating current thin-film electroluminescent (ACTFEL) device and/or an ACTFEL device includes the phosphor material sandwiched between a pair of dielectric layers suitable to substantially prevent DC current from flowing therebetween. The phosphor material is comprised of, in one aspect of the present invention, the formula MIIS:Eu,Cu, wherein MII is strontium, S is sulphur, Eu is europium, Cu is copper. In another aspect of the present invention, the phosphor material is comprised of the formula MIIS:Eu,Cu, wherein MII is calcium, S is sulphur, Eu is europium, Cu is copper. In yet another aspect of the present invention, the phosphor material is comprised of the formula MIIS:Eu,Cu, wherein MII is strontium and calcium, S is sulphur, Eu is europium, Cu is copper. In a further aspect of the present invention, the phosphor material is comprised of the formula MIIS:Mn,Cu, wherein MII is strontium, S is sulphur, Mn is manganese, Cu is copper.

Abstract: A light emitting phosphor having improved luminance is incorporated into an ACTFEL device which includes a phosphor layer having the formula MIIS:Cu,Ag where MII is taken from the group calcium, strontium, barium and magnesium, S is sulfur, Cu is copper, and Ag is silver.

Abstract: The luminance of a phosphor suitable for an alternating current thin-film electroluminescent device is substantially improved according to the present invention by including an alkali halide. The alkali halide included within the bulk of the phosphor material results in providing a significant number of trapping states which trap free electrons within the phosphor material. The addition of the trapping states (added defects) within the bulk tend to control the electrical and optical characteristics of the phosphor material. This reduces asymmetric light output characteristics of traditional phosphor material, reduces asymmetric current movement within the phosphor material, and decreases the influence of the interfaces between the phosphor material and insulating materials resulting in decreased aging and increased brightness.

Abstract: A light emitting phosphor having improved luminance is incorporated into an ACTFEL device having front and rear electrode sets, a pair of insulators sandwiched between the front and rear electrode sets, and a thin film electroluminescent laminar stack which includes a phosphor layer having the formula M.sup.II S:D,H where M.sup.II is taken from the group calcium, strontium, barium, and magnesium, S=sulfur, D is taken from the group copper, lead, gold, silver, magnesium, antimony, bismuth and arsenic, and H is taken from the group fluorine, chlorine, bromine, and iodine. Deep blue and green chromaticity phosphors may be obtained through selection of multiple co-dopants and adjusting their relative concentrations.

Abstract: A light emitting phosphor having improved luminance is incorporated into an ACTFEL device having front and rear electrode sets, a pair of insulators sandwiched between the front and rear electrode sets, and a thin film electroluminescent laminar stack which includes a phosphor layer having the formula M.sup.II S:D,H,F where M.sup.II is taken from the group calcium, strontium, barium, and magnesium, S=sulfur, D is taken from the group copper, lead, gold, silver, magnesium, antimony, bismuth and arsenic, H is taken from the group fluorine, chlorine, bromine, and iodine, and F is taken from the group gallium, indium, aluminum, germanium, silicon, lanthanum, scandium, and yttrium. Deep blue and green chromaticity phosphors may be obtained through selection of multiple co-dopants and adjusting their relative concentrations.

Abstract: A light emitting phosphor having improved luminance is incorporated into an ACTFEL device having front and rear electrode sets, a pair of insulators sandwiched between the front and rear electrode sets, and a thin film electroluminescent laminar stack which includes a phosphor layer having the formula M.sup.II S:D,H,F where M.sup.II is taken from the group calcium, strontium, barium, and magnesium, S=sulfur, D is taken from the group copper, lead, gold, silver, magnesium, antimony, bismuth and arsenic, H is taken from the group fluorine, chlorine, bromine, and iodine, and F is taken from the group gallium, indium, aluminum, germanium, silicon, lanthanum, scandium, and yttrium. Deep blue and green chromaticity phosphors may be obtained through selection of multiple co-dopants and adjusting their relative concentrations.

Abstract: An electroluminescent phosphor is sandwiched by a pair of insulating layers which are sandwiched by a pair of electrode layers to provide an AC TFEL device. The phosphor consists of a host material and an activator dopant that is preferably a rare earth. The host material is an alkaline earth sulfide, an alkaline earth selenide or an alkaline earth sulfide selenide that includes a Group 3A metal selected from aluminum, gallium and indium. The phosphor is preferably fabricated by first depositing a layer of the alkaline earth sulfide, alkaline earth selenide or alkaline earth sulfide selenide including the rare earth dopant therein, depositing thereon an overlayer selected from an alkaline earth thiogallate, an alkaline earth thioindate, an alkaline earth thioaluminate, an alkaline earth selenoaluminate, an alkaline earth selenoindate, or an alkaline earth selenogallate. The two layers are annealed at a temperature preferably between 750.degree. and 850.degree. C.

Abstract: A novel thin-film electroluminescent (TFEL) structure for emitting light in response to the application of an electric field is disclosed. The TFEL structure includes first and second electrode layers sandwiching a TFEL stack, the stack including first and second insulator layers and a phosphor layer that includes an alkaline earth thiogallate doped with oxygen.

Abstract: An AC thin film electroluminescent (TFEL) device includes a multilayer phosphor for emitting white light having improved emission intensity in the blue region of the spectrum. The multilayer stack consists of an inverted structure thin film stack having a red light emitting manganese doped zinc sulfide (ZnS:Mn) layer disposed on a first insulating layer; a blue-green light emitting cerium doped strontium sulfide (SrS:Ce) layer disposed on the red light emitting layer; and a blue light emitting cerium activated thiogallate phosphor (Sr.sub.x Ca.sub.1-x Ga.sub.2 S.sub.4 :Ce) layer disposed on the blue-green light emitting layer. The manganese doped zinc sulfide layer acts as a nucleating layer that lowers the threshold voltage, and the cerium activated thiogallate phosphor layer provides a moisture barrier for the hydroscopic cerium doped strontium sulfide layer. The white light from the multilayer phosphor can be appropriately filtered to produce any desired color.

Abstract: A TFEL structure is disclosed that includes first and second electrode layers sandwiching a TFEL stack including at least one insulator layer and a novel three layer laminate structure. The three-layer laminate structure includes an alkaline earth thiogallate phosphor layer, a nucleating layer and an injection layer. The nucleating layer lies between the phosphor layer and the injection layer. The injection layer provides a charge injection function through the nucleating layer for the thiogallate phosphor layer which is of high crystallinity at its interface with the nucleating layer. A preferred injection layer includes indium, for example as the metal or as indium tin oxide. The best material for the nucleating layer is zinc sulfide.

Abstract: A multi-source reactive deposition process for preparing a phosphor layer for an AC TFEL device having the chemical formula M.sup.II M.sup.III.sub.2 X.sub.4 :RE, where M.sup.II is a group II metal taken from the group magnesium, calcium, strontium and barium, M.sup.III is a group III metal taken from the group aluminum, gallium and indium, X is taken from the group sulfur and selenium, and RE comprises a rare earth activator dopant taken from the group cerium and europium is disclosed. The phosphor film is formed in crystalline form on a substrate heated to a temperature between 400.degree. and 800.degree. C. by depositing more than one deposition source chemical where at least one of the deposition source chemicals of the group II metal or the group III metal is a compound.