Abstract: An integrated circuit FM detector which compensates for variations in semiconductor manufacturing process and temperature employs a pair of serially connected switched capacitor-operational amplifier combinations. The first combination is a frequency to voltage converter which uses a switched capacitor input circuit which is clocked at the frequency of the input signal, an operational amplifier and a feedback resistor. The second combination is a compensation circuit which uses an input resistor, a feedback switched capacitor circuit and an operational amplifier. The feedback switched capacitor circuit is clocked at a fixed rate. Reversal of the roles of the resistor and the switched capacitor in the first and second combinations compensates for both temperature and manufacturing process variations.

Abstract: A Phase Locked Loop (PLL) circuit includes a compensation circuit which corrects for non-linear sensitivity of a varactor of a voltage controlled oscillator (VCO) which is part of the circuit. The varactor is employed as a capacitance tuning element. The compensation circuit controls the sensitivity of a charging/discharging circuit (a charge pump) of the PLL circuit with a feedback signal which is derived from an input to the VCO. The sensitivity characteristic of the charge pump is made the complement of the non-linear portion of the VCO sensitivity characteristic.

Abstract: An audio processor for adaptively rejecting undesired noise and interference in an audio input which includes a variable Q, 10 kHz switched capacitor notch filter. The Q of the notch filter is varied by a control loop responsive to the 10 kHz content of the audio signal. The notch filter includes a summer section that is clocked at a predetermined frequency, and an integrator section which is clocked at a multiple of the predetermined frequency in order to prevent center frequency variation with changes in Q of the notch filter.