Abstract: A wireless communication device (100) may include a receiver (110), a memory (104), a digital-to-analog converter (128), an audio playback system (124) and other features. A dynamic range controller (130) selectively generates control signals to adjust, at least in part, the operational dynamic range of the digital-to-analog converter (128) for digital signals received by the receiver (110) or stored in the memory (104). The selection of dynamic range is based on identifying a characteristic. In one embodiment, the control signals are used to selectively operate the digital-to-analog converter (128) at a particular dynamic range based on a sampling rate of a received digital audio signal.

Abstract: A frequency response adjuster for a frequency responsive circuit, and a method for tuning a frequency response of a circuit, are disclosed. The adjuster may include a time constant sensor, wherein a charging state of the frequency responsive circuit may be measured by, and output from, the time constant sensor as a first voltage, a converter that samples the first voltage and outputs a second voltage resultant from a conversion of the first voltage by the converter, an array of trimming components, and a selector that utilizes the second voltage to select at least one trimming component from the array of trimming components. The method includes the steps of sensing a time constant of the circuit, outputting the sensing as a first voltage, sampling the first voltage over a fixed interval, converting the sampled first voltage to a second voltage, and selecting, utilizing the second voltage, at least one trimming component from an array of trimming components.

Abstract: A digital to analog converter augmented with Direct Charge Transfer (DCT) techniques. A digital to analog converter augmented with DCT and CDS techniques. A digital to analog converter augmented with Postfilter Droop Compensation.

Abstract: An on-chip detection circuit automatically detects when an external switch has been activated. When the device is initialized, the detection circuit measures the operating current and coverts the information into an analog voltage. The analog voltage is then processed through an on-chip analog-to-digital converter and the digitized result is stored as a reference value. To sense the open and close action of the off-chip mechanical switch, the device then takes a sample of the operating current periodically, digitizes this information and compares the sampled value to the reference value. A change in value larger than some predetermined level indicates the external switch has been activated.

Abstract: A frequency response adjuster for a frequency responsive circuit, and a method for tuning a frequency response of a circuit, are disclosed. The adjuster may include a time constant sensor, wherein a charging state of the frequency responsive circuit may be measured by, and output from, the time constant sensor as a first voltage, a converter that samples the first voltage and outputs a second voltage resultant from a conversion of the first voltage by the converter, an array of trimming components, and a selector that utilizes the second voltage to select at least one trimming component from the array of trimming components. The method includes the steps of sensing a time constant of the circuit, outputting the sensing as a first voltage, sampling the first voltage over a fixed interval, converting the sampled first voltage to a second voltage, and selecting, utilizing the second voltage, at least one trimming component from an array of trimming components.

Abstract: The present invention encompasses a mobile station comprising a transmitter for transmitting outgoing signals from the mobile station and a receiver for receiving incoming signals, the receiver coupled to the transmitter and having N subreceivers, where N is an integer greater than one and each of the N subreceivers may independently be tuned to a desired frequency.

Abstract: A multi-stage circuit that includes a number of stages, with at least one stage being of a first type and at least one stage being of a second type. Each stage receives either a circuit input signal or an output signal from a preceding stage, processes (e.g., filters) the received signal, and provides a respective output signal. Each first type (or second type) stage operates based on one or more clock signals having a frequency of fS (or fS/N), where fS is the sampling frequency and N is an integer greater than one. Each first type stage may be implemented with a correlated double-sampling circuit, an auto-zeroing circuit, or a chopper stabilization circuit. Each second type stage may be implemented with a multi-sampling (i.e., double-sampling or higher order sampling) circuit. The multi-stage circuit may be designed to implement a lowpass filter, a &Dgr;&Sgr; ADC, or some other circuit.

Abstract: The present invention encompasses a mobile station comprising a transmitter for transmitting outgoing signals from the mobile station and a receiver for receiving incoming signals, the receiver coupled to the transmitter and having N subreceivers, where N is an integer greater than one and each of the N subreceivers may independently be tuned to a desired frequency.

Abstract: A bandpass &Sgr;&Dgr; ADC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, a two-path interleaved resonator, or a four-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a &Sgr;&Dgr; ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 &Sgr;&Dgr; ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application.

Abstract: Techniques for processing incoming signals conforming to a plurality of standards or communication formats with a single baseband receive section are disclosed. In one aspect, a plurality of analog processing components are adjusted in response to a format select signal, set according to one of a plurality of supported formats or standards. In another aspect, the operating mode of an A/D converter is tuned in response to the format select signalIn yet another aspect, the response characteristics of a jammer filter are tuned in response to the format select signal. In yet another aspect, the adjustment of the plurality of analog processing components is carried out by varying the frequency of a sample clock in response to the format select signal. Various other aspects are also presented. These aspects have the benefit of allowing a single baseband receive section to be deployed to process analog signals conforming to a plurality of communications standards or formats, in a power and area efficient manner.

Abstract: Techniques for fabricating analog and digital circuits on separate dies and stacking and integrating the dies within a single package to form a mixed-signal IC that provides many benefits. In one aspect, the analog and digital circuits are implemented on two separate dies using possibly different IC processes suitable for these different types of circuits. The analog and digital dies are thereafter integrated (stacked) and encapsulated within the single package. Bonding pads are provided to interconnect the dies and to connect the dies to external pins. The bonding pads may be located and arranged in a manner to provide the required connectivity while minimizing the amount of die area required to implement the pads. In another aspect, the die-to-die connectivity may be tested in conjunction with a serial bus interface.

Abstract: A multi-stage circuit that includes a number of stages, with at least one stage being of a first type and at least one stage being of a second type. Each stage receives either a circuit input signal or an output signal from a preceding stage, processes (e.g., filters) the received signal, and provides a respective output signal. Each first type (or second type) stage operates based on one or more clock signals having a frequency of fS (or fS/N), where fS is the sampling frequency and N is an integer greater than one. Each first type stage may be implemented with a correlated double-sampling circuit, an auto-zeroing circuit, or a chopper stabilization circuit. Each second type stage may be implemented with a multi-sampling (i.e., double-sampling or higher order sampling) circuit. The multi-stage circuit may be designed to implement a lowpass filter, a &Dgr;&Sgr; ADC, or some other circuit.

Abstract: Techniques for fabricating analog and digital circuits on separate dies and stacking and integrating the dies within a single package to form a mixed-signal IC that provides many benefits. In one aspect, the analog and digital circuits are implemented on two separate dies using possibly different IC processes suitable for these different types of circuits. The analog and digital dies are thereafter integrated (stacked) and encapsulated within the single package. Bonding pads are provided to interconnect the dies and to connect the dies to external pins. The bonding pads may be located and arranged in a manner to provide the required connectivity while minimizing the amount of die area required to implement the pads. In another aspect, the die-to-die connectivity may be tested in conjunction with a serial bus interface.

Abstract: A wireless communication device (100) may include a receiver (110), a memory (104), a digital-to-analog converter (128), an audio playback system (124) and other features. A dynamic range controller (130) selectively generates control signals to adjust, at least in part, the operational dynamic range of the digital-to-analog converter (128) for digital signals received by the receiver (110) or stored in the memory (104). The selection of dynamic range is based on identifying a characteristic. In one embodiment, the control signals are used to selectively operate the digital-to-analog converter (128) at a particular dynamic range based on a sampling rate of a received digital audio signal.

Abstract: A control mechanism that can be used to control a &Sgr;&Dgr; ADC to provide the required level of performance while reducing power consumption. The &Sgr;&Dgr; ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a &Sgr;&Dgr; ADC that is similar to the &Sgr;&Dgr; ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor.

Abstract: A bias circuit is described for use in biasing an operational amplifier to maintain a constant transconductance divided by load capacitance (i.e. a constant gm/CL) despite temperature and process variations and despite body effects. In one example, the bias circuit includes a pair of current source devices and a switched capacitor (SC) equivalent resistor circuit for developing an equivalent resistance between the current source devices. The equivalent resistor circuit includes a sampling capacitor. First and second clock inputs are connected to the capacitor providing non-overlapping clock signals at a predetermined sampling frequency to establish a resistance equivalent. By providing an SC equivalent resistor circuit clocked by non-overlapping fixed clock signals, the gm/CL of the bias circuit is maintained substantially constant. Hence, a fixed bandwidth is maintained within the operational amplifier being biased.

Abstract: A bias cell for use in biasing all NMOS differential pair is configured to substantially eliminate variations in transconductance caused by body effects. In one example, a voltage threshold mismatch between NMOS devices of the bias cell is substantially eliminated to thereby reduce variations in transconductance caused by body effects. To reduce the voltage threshold mismatch, the bias cell includes a transconductance-setting resistor connected between gates of a pair of current source devices. Circuitry is connected to the resistor for applying a voltage across the resistor. A bias line connects a signal output from the bias circuit to the differential pair.