Patents by Inventor Shahab Siddiqui
Shahab Siddiqui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9006837Abstract: A complementary metal oxide semiconductor structure including a scaled 0 and a scaled pFET which do not exhibit an increased threshold voltage and reduced mobility during operation is provided. The method includes forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack can also be plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and an nFET threshold voltage adjusted species, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and a pFET threshold voltage adjusted species.Type: GrantFiled: March 11, 2013Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Dechao Guo, Siddarth A. Krishnan, Unoh Kwon, Carl J. Radens, Shahab Siddiqui
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Patent number: 9006064Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.Type: GrantFiled: March 11, 2013Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Barry P. Linder, Shahab Siddiqui
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Publication number: 20150069525Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.Type: ApplicationFiled: November 14, 2014Publication date: March 12, 2015Inventors: Charlotte D. Adams, Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui
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Patent number: 8952460Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.Type: GrantFiled: November 12, 2013Date of Patent: February 10, 2015Assignee: International Business Machines CorporationInventors: MaryJane Brodsky, Murshed M. Chowdhury, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan, Shreesh Narasimha, Shahab Siddiqui
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Patent number: 8941177Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.Type: GrantFiled: June 27, 2012Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Charlotte DeWan Adams, Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui
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Patent number: 8836037Abstract: A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.Type: GrantFiled: August 13, 2012Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Takashi Ando, Min Dai, Martin M. Frank, Barry P. Linder, Shahab Siddiqui
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Publication number: 20140252503Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Barry P. Linder, Shahab Siddiqui
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Patent number: 8809152Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.Type: GrantFiled: November 18, 2011Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: MaryJane Brodsky, Murshed M. Chowdhury, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan, Shreesh Narasimha, Shahab Siddiqui
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Publication number: 20140170844Abstract: A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein.Type: ApplicationFiled: January 29, 2014Publication date: June 19, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Dechao Guo, Siddarth A. Krishnan, Unoh Kwon, Carl J. Radens, Shahab Siddiqui
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Publication number: 20140061819Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.Type: ApplicationFiled: November 12, 2013Publication date: March 6, 2014Applicant: International Business Machines CorporationInventors: MaryJane Brodsky, Murshed M. Chowdhury, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan, Shreesh Narasimha, Shahab Siddiqui
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Publication number: 20140042546Abstract: A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.Type: ApplicationFiled: August 13, 2012Publication date: February 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Min Dai, Martin M. Frank, Barry P. Linder, Shahab Siddiqui
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Patent number: 8643115Abstract: A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided.Type: GrantFiled: January 14, 2011Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Dechao Guo, Siddarth A. Krishnan, Unoh Kwon, Carl J. Radens, Shahab Siddiqui
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Publication number: 20140001570Abstract: A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MaryJane Brodsky, Michael P. Chudzik, Min Dai, Joseph F. Shepard, JR., Shahab Siddiqui, Yanfeng Wang, Jinping Liu
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Publication number: 20140001575Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charlotte DeWan Adams, Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui
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Publication number: 20130330843Abstract: A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH3); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.Type: ApplicationFiled: June 7, 2012Publication date: December 12, 2013Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Min Dai, Jinping Liu, Paul A. Ronsheim, Joseph F. Shepard, JR., Shahab Siddiqui
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Publication number: 20130293831Abstract: Ophthalmic lens molds made from one or more thermoplastic polymer having a low level of UV light transmittance (UV % T) ophthalmic lenses including silicone hydrogel contact lenses molded using these thermoplastic polymer having low UV % T, and methods of manufacturing ophthalmic lenses by cast molding a polymerizable composition in mold members formed of these thermoplastic polymers having low UV % T and curing the polymerizable composition using UV light are described.Type: ApplicationFiled: July 8, 2011Publication date: November 7, 2013Applicant: COOPERVISION INTERNATIONAL HOLDING COMPANY, LPInventors: Lee Darren Norris, Edyta S. Bialek, Sarah L. Almond, David Robert Morsley, A.K.M. Shahab Siddiqui, Richard C. Rogers, Ian Bruce, Benjamin S. Sheader
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Patent number: 8492290Abstract: A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 ? to 10 ?.Type: GrantFiled: June 21, 2011Date of Patent: July 23, 2013Assignees: International Business Machines Corporation, Globalfoundries Inc.Inventors: Michael P. Chudzik, Min Dai, Joseph F. Shepard, Jr., Shahab Siddiqui, Jinping Liu
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Publication number: 20130162942Abstract: Ophthalmic lens molds made from one or more thermoplastic polymers with average polarities from about 1% to about 7%, ophthalmic lenses including silicone hydrogel contact lenses molded using these less polar thermoplastic polymers, and related methods are described. When the molds are used to cast mold silicone hydrogel contact lenses, the resulting polymerized lens bodies have ophthalmically acceptably wettable surfaces.Type: ApplicationFiled: July 8, 2011Publication date: June 27, 2013Applicant: COOPERVISION INTERNATIONAL HOLDING COMPANY, LPInventors: Lee Darren Norris, Edyta S. Bialek, Sarah L. Almond, David Robert Morsley, A.K.M. Shahab Siddiqui, Richard C. Rogers, Ian Bruce, Benjamin S. Sheader
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Publication number: 20130155372Abstract: Methods of manufacturing contact lenses using ophthalmic lens molds having a molding surface comprising a thermoplastic polymer, the molding surface having a percent polarity from 3% to 20% and a surface energy from about 25 mN/m to about 40 mN/m to cast mold a polymerizable composition having a surface tension from about 20 mN/m to about 25 mN/m, wherein a surface energy differential of the surface tension of the polymerizable composition less the surface energy of the molding surface less than or equal to zero (0); and silicone hydrogel contact lens bodies so manufactured are described.Type: ApplicationFiled: July 29, 2011Publication date: June 20, 2013Applicant: COOPERVISION INTERNATIONAL HOLDING COMPANY, LPInventors: A.K.M. Shahab Siddiqui, David Robert Morsley, Sarah L. Almond, Richard C. Rogers, Ian Bruce, Lee Darren Norris, Edyta S. Bialek, Benjamin S. Sheader
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Publication number: 20130126986Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.Type: ApplicationFiled: November 18, 2011Publication date: May 23, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MaryJane Brodsky, Murshed M. Chowdhury, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan, Shreesh Narasimha, Shahab Siddiqui