Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region in a gate space, one or more conductive layers are formed over the gate dielectric layer, a seed layer is formed over the one or more conductive layers, an upper portion of the seed layer is treated by introducing one or more elements selected from the group consisting of oxygen, nitrogen and fluorine, and a W layer is selectively formed on a lower portion of the seed layer that is not treated to fully fill the gate space with bottom-up filling approach.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and forming a first plurality of protruding fins and a second protruding fin over the isolation regions. The first plurality of protruding fins include an outer fin farthest from the second protruding fin, and an inner fin closest to the second protruding fin. The method further includes etching the first plurality of protruding fins to form first recesses, growing first epitaxy regions from the first recesses, wherein the first epitaxy regions are merged to form a merged epitaxy region, etching the second protruding fin to form a second recess, and growing a second epitaxy region from the second recess. A top surface of the merged epitaxy region is lower on a side facing toward the second epitaxy region than on a side facing away from the second epitaxy region.

Abstract: A gate structure of a field effect transistor includes a first gate dielectric layer, a second gate dielectric layer, and one or more conductive layers disposed over the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer is separated from the second gate dielectric layer by a gap filled with a diffusion blocking layer.

Abstract: A semiconductor device includes semiconductor nanostructures disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor nanostructures, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor nanostructures, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor nanostructures, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.

Abstract: A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.

Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, and a source/drain (S/D) region adjacent to the gate structure. The S/D region can include first and second side surfaces separated from each other. The S/D region can further include top and bottom surfaces between the first and second side surfaces. A first separation between the top and bottom surfaces can be greater than a second separation between the first and second side surfaces.

Abstract: Semiconductor device manufacturing includes forming fins over substrate extending in first direction. Gate is formed over fin's first portion, gate extends in second direction crossing first. Fin mask layer formed on fin sidewalls. Fin second portions are recessed, wherein second portions are located on opposing gate sides. Epitaxial source/drains are formed over recessed fins. Epitaxial source/drain structures include first layer having first dopant concentration, second layer having second dopant concentration, and third layer having third dopant concentration. Third concentration is greater than second concentration, second concentration is greater than first concentration.

Abstract: Provided are methods of manufacturing an integrated circuit device including depositing a conductive layer on a substrate, patterning the conductive layer to expose regions of the conductive layer, etching a first portion of the exposed regions of the conductive layer, forming a first passivation layer on a sidewall of the first etched portion, etching a second portion of the exposed regions of the conductive layer, and forming a second passivation layer on a sidewall of the second etched portion.

Abstract: Embodiments of the present disclosure provide methods for forming merged source/drain features from two or more fin structures. The merged source/drain features according to the present disclosure have a merged portion with an increased height percentage over the overall height of the source/drain feature. The increase height percentage provides an increased landing range for source/drain contact features, therefore, reducing the connection resistance between the source/drain feature and the source/drain contact features. In some embodiments, the emerged source/drain features include one or more voids formed within the merged portion.

Abstract: Implementations described herein provide a method that includes implanting a dopant and carbon in a portion of a substrate of a semiconductor device. The method also includes depositing a first silicon-based layer on the portion of the substrate, the first silicon-based layer reacting with the carbon to form a diffusion region on the portion of the substrate. The method further includes forming a recessed portion of the semiconductor device, the recessed portion extending through the first silicon-based layer and the diffusion region and partially extending into the portion of the substrate. The method additionally includes depositing a second silicon-based layer within the recessed portion. The method further includes etching one or more portions of the second silicon-based layer and the portion of the substrate to form a set of fin structures that include the second silicon-based layer and the portion of the substrate having the dopant and the carbon implanted.

Abstract: A method includes forming a first fin and a second fin over a substrate, depositing an isolation material surrounding the first and second fins, forming a gate structure along sidewalls and over upper surfaces of the first and second fins, recessing the first and second fins outside of the gate structure to form a first recess in the first fin and a second recess in the second fin, epitaxially growing a first source/drain material protruding from the first and second recesses, and epitaxially growing a second source/drain material on the first source/drain material, wherein the second source/drain material grows at a slower rate on outermost surfaces of opposite ends of the first source/drain material than on surfaces of the first source/drain material between the opposite ends of the first source/drain material, and wherein the second source/drain material has a higher doping concentration than the first source/drain material.

Abstract: An embodiment device includes: an isolation region on a substrate; a first fin extending above a top surface of the isolation region; a gate structure on the first fin; and an epitaxial source/drain region adjacent the gate structure, the epitaxial source/drain region having a first main portion and a first projecting portion, the first main portion disposed in the first fin, the first projecting portion disposed on a first sidewall of the first fin and beneath the top surface of the isolation region.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.

Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

Abstract: In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer.

Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a sacrificial gate over an active region of a substrate. The sacrificial gate is removed to form an opening. A gate dielectric layer is formed on sidewalls and a bottom of the opening. A first work function layer is formed over the gate dielectric layer in the opening. A first protective layer is formed over the first work function layer in the opening. A first etch process is performed to widen an upper portion of the opening. The opening is filled with a conductive material.

Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.

Abstract: A method includes forming a first fin and a second fin over a substrate, depositing an isolation material surrounding the first and second fins, forming a gate structure along sidewalls and over upper surfaces of the first and second fins, recessing the first and second fins outside of the gate structure to form a first recess in the first fin and a second recess in the second fin, epitaxially growing a first source/drain material protruding from the first and second recesses, and epitaxially growing a second source/drain material on the first source/drain material, wherein the second source/drain material grows at a slower rate on outermost surfaces of opposite ends of the first source/drain material than on surfaces of the first source/drain material between the opposite ends of the first source/drain material, and wherein the second source/drain material has a higher doping concentration than the first source/drain material.