Abstract: Some implementations described herein provide a nanostructure transistor and methods of formation. The nanostructure transistor includes concave-shaped regions at ends of a plurality of channel layers. The nanostructure transistor further includes convex-shaped portions of an epitaxial material, included as part of a source/drain region of the nanostructure transistor, that extend into the concave-shaped regions. Masking, etching, and cleaning operations, performed after deposition of a buffer layer, may form the concave-shaped regions.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes one or more semiconductor layers, an interfacial layer surrounding at least one semiconductor layer of the one or more semiconductor layers, a work function metal disposed over the interfacial layer, and a high-K (HK) dielectric layer disposed between the interfacial layer and the work function metal. The HK dielectric layer includes a first dopant region adjacent to a first interface of the HK dielectric layer and the interfacial layer, wherein the first dopant region comprises first dopants having a first polarity. The HK dielectric layer also includes a second dopant region adjacent to a second interface of the HK dielectric layer and the work function metal, wherein the second dopant region comprises second dopants having a second polarity opposite the first polarity.

Abstract: A method for forming a semiconductor device structure is described. The method includes forming a first semiconductor layer over a substrate in a processing chamber and performing a purge process. The purge process includes flowing a chlorine-containing gas into the processing chamber. The method further includes forming a second semiconductor layer over the first semiconductor layer, and an interface region is formed between the first and second semiconductor layers.

Abstract: Wavy-shaped epitaxial source/drain structures for multigate devices and methods of fabrication thereof are disclosed herein. An exemplary device includes a first fin and a second fin extending lengthwise along a first direction. The first fin and the second fin each have a non-recessed portion and a recessed portion. A gate extends lengthwise along a second direction that is different than the first direction. The gate wraps the non-recessed portion of the first fin and the non-recessed portion of the second fin. A merged epitaxial source/drain is on the recessed portion of the first fin and the recessed portion of the second fin. A source/drain contact is on the merged epitaxial source/drain. The source/drain contact and the merged epitaxial source/drain have a V-shaped interface therebetween. The source/drain contact extends below tops of the non-recessed portions of the first fin and the second fin.

Abstract: The present disclosure describes a method of forming a semiconductor device having epitaxial structures with optimized dimensions. The method includes forming first and second fin structures on a substrate, forming a spacer layer on the first and second fin structures, forming a first spacer structure adjacent to the first fin structure, and forming a first epitaxial structure adjacent to the first spacer structure. The first and second fin structures are separated by an isolation layer. The first spacer structure has a first height above the isolation layer. The method further includes forming a second spacer structure adjacent to the second fin structure and forming a second epitaxial structure adjacent to the second spacer structure. The second spacer structure has a second height above the isolation layer greater than the first height. The second epitaxial structure includes a type of dopant different from the first epitaxial structure.

Abstract: Embodiments of the present disclosure provide methods for forming merged source/drain features from two or more fin structures. The merged source/drain features according to the present disclosure have a merged portion with an increased height percentage over the overall height of the source/drain feature. The increase height percentage provides an increased landing range for source/drain contact features, therefore, reducing the connection resistance between the source/drain feature and the source/drain contact features. In some embodiments, the emerged source/drain features include one or more voids formed within the merged portion.

Abstract: A method includes forming a semiconductor fin protruding from a semiconductor substrate. The semiconductor fin has an epitaxial portion and a mesa portion under the epitaxial portion. The epitaxial portion has a plurality of channel layers interleaved with a plurality of sacrificial layers. The semiconductor substrate has a top surface in (110) crystal plane. The method also includes forming a dummy gate structure across the semiconductor fin, removing at least the epitaxial portion of the semiconductor fin in a region adjacent the dummy gate structure to form a recess, epitaxially growing a buffer semiconductor region in the recess, epitaxially growing a source/drain feature on the buffer semiconductor region, and replacing the dummy gate structure with a metal gate structure. The buffer semiconductor region has a top surface in (110) crystal plane.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.

Abstract: A semiconductor device having a gate structure and a method of forming same are provided. The semiconductor device includes a substrate and a gate structure over the substrate. The substrate has a first region and a second region. The gate structure extends across an interface between the first region and the second region. The gate structure includes a first gate dielectric layer over the first region, a second gate dielectric layer over the second region, a first work function layer over the first gate dielectric layer, a barrier layer along a sidewall of the first work function layer and above the interface between the first region and the second region, and a second work function layer over the first work function layer, the barrier layer and the second gate dielectric layer. The second work function layer is in physical contact with a top surface of the first work function layer.

Abstract: A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

Abstract: The present disclosure describes method to form a semiconductor device having a gate dielectric layer with controlled doping. The method includes forming a gate dielectric layer on a fin structure, forming a diffusion barrier layer on the gate dielectric layer, and forming a dopant source layer on the diffusion barrier layer. The gate dielectric layer includes an interfacial layer on the fin structure and a high-k dielectric layer on the interfacial layer. A dopant of the dopant source layer diffuses into the gate dielectric layer. The method further includes doping a portion of the interfacial layer with the dopant and removing the dopant source layer. The portion of the interfacial layer is adjacent to the high-k dielectric layer.

Abstract: A method includes etching a silicon layer in a wafer to form a first trench in a first device region and a second trench in a second device region, performing a pre-clean process on the silicon layer, performing a baking process on the wafer, and performing an epitaxy process to form a first silicon germanium region and a second silicon germanium region in the first trench and the second trench, respectively. The first silicon germanium region and the second silicon germanium region have a loading in a range between about 5 nm and about 30 nm.

Abstract: A semiconductor structure includes a substrate, a semiconductor fin connected to the substrate, an epitaxial layer disposed over the semiconductor fin, and a silicide feature over and in contact with the epitaxial layer. The epitaxial layer including silicon germanium and further includes gallium in an upper portion of the epitaxial layer that is in contact with the silicide feature.

Abstract: A semiconductor structure includes a first transistor adjacent a second transistor. The first transistor includes a first gate metal layer over a gate dielectric layer, and the second transistor includes a second gate metal layer over the gate dielectric layer. The first and the second gate metal layers include different materials. The semiconductor structure further includes a first barrier disposed horizontally between the first gate metal layer and the second gate metal layer. One of the first and the second gate metal layers includes aluminum, and the first barrier has low permeability for aluminum. A bottom surface of the first gate metal layer is directly on a top surface of the first barrier.

Abstract: Some implementations described herein provide techniques and semiconductor devices in which a buffer region is formed under a source/drain region of a device. The buffer region is configured to reduce, prevent, and/or block migration of dopants from the source/drain region to other areas of the device, such a mesa region of an adjacent fin structure. In some implementations, a sidewall layer is between the buffer region and the mesa region. Additionally, or alternatively, a dielectric region including a dielectric gas may be between the buffer region and the source/drain region.

Abstract: Some implementations described herein provide techniques and apparatuses for forming insulator layers in or on a semiconductor substrate prior to forming epitaxial layers within source/drain regions of a fin field-effect transistor. The epitaxial layers may be formed over the insulator layers to reduce electron tunneling between the source/drain regions of the fin field-effect transistor. In this way, a likelihood of leakage into the semiconductor substrate and/or between the source/drain regions of the fin field-effect transistor is reduced.

Abstract: A FinFET device and a method of forming the same are provided. The method includes forming semiconductor strips over a substrate. Isolation regions are formed over the substrate and between adjacent semiconductor strips. A first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. The first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. A second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. The second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. The reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. The fins extend away from topmost surfaces of the isolation regions.

Abstract: In some implementations, a buffer layer is formed under a source/drain region of a device. A shape of the buffer layer may include a curved top surface having a height that extends to increase coverage of nanosheets of a fin structure of the device. The shape also includes regions having widths that extend towards shallow trench isolation regions of the device. The shape reduces a likelihood of dopants diffusing from the source/drain region into a mesa region of the fin structure. As a result, a performance of the device may be increased by decreasing short channel effects, decreasing an off-current of the device, and decreasing leakage within the device, among other examples.

Abstract: Some implementations described herein provide a semiconductor device and methods of formation. The semiconductor device may include one or more device types, such as a static random access memory device type, a ring oscillator device type, and/or an input/output device type. A device type may include an n-type metal oxide semiconductor nanostructure transistor and a p-type metal oxide semiconductor nanostructure transistor. In such a case, nanostructure channels of the n-type metal oxide semiconductor nanostructure transistor may have a width that is lesser relative to a width of nanostructure channels of the p-type metal oxide semiconductor nanostructure transistor. Additionally, or alternatively, other properties of the nanostructure transistors, such as a gate length or a width of a source/drain region, may vary based on the device type.