Patents by Inventor Shahram Mostafazadeh

Shahram Mostafazadeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6975038
    Abstract: An integrated circuit package with lead fingers with a footprint on the order of the integrated circuit footprint is provided. A lead frame may be made from a metal sheet, which may be stamped or etched. The lead frame provides a plurality of posts and a connecting sheet connecting the plurality of posts. Dice are adhesively mounted to the plurality of posts. The dice have a conductive side with a plurality of conducting pads where each conducting pad is electrically and mechanically connected to a post. An encapsulating material is placed over the dice and lead frame, with the connecting sheet keeping the encapsulating material on one side of the lead frame. Parts of the connecting sheet are then removed, electrically isolating the posts. The integrated circuit packages formed by the encapsulated dice and leads may be tested as a panel, before the integrated circuit packages are singulated.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: December 13, 2005
    Assignee: National Semiconductor Corporation
    Inventor: Shahram Mostafazadeh
  • Patent number: 6936929
    Abstract: Multichip packages and methods for making same. The present invention generally allows for either the back of a flipchip, the back of a mother die, or both to be exposed in a multichip package. When the mother die is connected to the package contacts, the back of the flip chip is higher than the electrical connections. Accordingly, the back of the flip chip can be exposed. Furthermore, if a temporary tape substrate is used with a leadframe panel that does not have a die attach pad, the package can be even thinner. Once the temporary tape substrate is removed, both the back of the flipchip and the back of the mother die will be exposed from the encapsulant.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: August 30, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Joseph O. Smith
  • Patent number: 6894376
    Abstract: Arrangements and methods of packaging integrated circuits in leadless leadframe packages configured for maximizing a die size are disclosed. The package is described having an exposed die attach pad and a plurality of exposed contacts formed from a common substrate material. The contacts, however, are thinned relative to the die attach pad. In one embodiment, an inner region of the contacts is thinned. In another embodiment, an outer region of the contacts is also thinned. A die is mounted on the die attach pad and wire bonded to the contacts. Since the inner region and sometimes together with the outer region of the contact are lower than the die attach pad being wire bonded to, the size of the die can be relatively increased to overhang over the contact, thereby maximizing the die size in the package. A plastic cap is molded over the die, contacts, and bonding wires while leaving the bottom surface of the contacts exposed.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: May 17, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Gerald Alexander Fields
  • Patent number: 6888228
    Abstract: In one aspect of the invention, a lead frame panel suitable for use in packaging an array of integrated circuits is described. The lead frame panel includes a matrix of tie bars that extend in substantially perpendicular rows and columns to define a two dimensional array of immediately adjacent device areas separated only by the tie bars. Each device area is suitable for use in an independent integrated circuit package and includes a die attach pad and a plurality of conductive contacts. In another aspect of the invention, a panel assembly suitable for use in simultaneously packaging a multiplicity of integrated circuits is described. The panel assembly includes a lead frame panel formed from a conductive sheet. The lead frame panel is patterned to define at least one two dimensional array of adjacent device areas. Each device area is suitable for use as part of an independent integrated circuit package and including a die and a plurality of contacts positioned around and electrically connected to the die.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: May 3, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Joseph O. Smith
  • Publication number: 20050039330
    Abstract: An apparatus and method for force mounting semiconductor packages onto printed circuit boards without the use of solder. The apparatus includes a substrate, a first integrated circuit die mounted onto the substrate, a housing configured to house the first integrated circuit die mounted onto the substrate, and a force mechanism configured to force mount the housing including the integrated circuit die and substrate onto a printed circuit board. The method includes mounting a first integrated circuit die onto a first surface of a substrate, housing the first integrated circuit die mounted onto the substrate in a housing, and using a force mechanism to force mount the housing including the first integrated circuit die mounted on the substrate onto a printed circuit board. According to various embodiments, the force mechanism includes one of the following types of force mechanisms clamps, screws, bolts, adhesives, epoxy, or Instrument housings or heat stakes.
    Type: Application
    Filed: September 30, 2004
    Publication date: February 24, 2005
    Applicant: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Joseph Smith
  • Publication number: 20040259288
    Abstract: Multichip packages and methods for making same. The present invention generally allows for either the back of a flipchip, the back of a mother die, or both to be exposed in a multichip package. When the mother die is connected to the package contacts, the back of the flip chip is higher than the electrical connections. Accordingly, the back of the flip chip can be exposed. Furthermore, if a temporary tape substrate is used with a leadframe panel that does not have a die attach pad, the package can be even thinner. Once the temporary tape substrate is removed, both the back of the flipchip and the back of the mother die will be exposed from the encapsulant.
    Type: Application
    Filed: July 13, 2004
    Publication date: December 23, 2004
    Applicant: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Joseph O. Smith
  • Patent number: 6823582
    Abstract: An apparatus and method for force mounting semiconductor packages onto printed circuit boards without the use of solder. The apparatus includes a substrate, a first integrated circuit die mounted onto the substrate, a housing configured to house the first integrated circuit die mounted onto the substrate, and a force mechanism configured to force mount the housing including the integrated circuit die and substrate onto a printed circuit board. The method includes mounting a first integrated circuit die onto a first surface of a substrate, housing the first integrated circuit die mounted onto the substrate in a housing, and using a force mechanism to force mount the housing including the first integrated circuit die mounted on the substrate onto a printed circuit board. According to various embodiments, the force mechanism includes one of the following types of force mechanisms clamps, screws, bolts, adhesives, epoxy, or Instrument housings or heat stakes.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: November 30, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Joseph O. Smith
  • Patent number: 6812125
    Abstract: A plastic or resin based substrate panel for use in semiconductor package is described. The substrate includes a matrix of conductive elements (e.g. conductive studs, balls or the like) which are held in place by a molding plastic material. The conductive elements form conductive vias through the substrate and have exposed top and bottom surfaces which serve as contacts or landing that may be used to electrically couple electrical devices to the substrate. The substrate panel may be populated with integrated circuits which in turn are electrically connected to the substrate, encapsulated and singulated to form a plurality of packaged integrated circuits.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: November 2, 2004
    Assignee: National Semiconductor Corporation
    Inventor: Shahram Mostafazadeh
  • Patent number: 6740961
    Abstract: A universal lead frame for mounting dice to form integrated circuit packages is provided. The lead frame may be made from a metal sheet, which may be stamped or etched. The lead frame provides a plurality of posts and a connecting sheet connecting the plurality of posts. Dice are adhesively mounted on to a first set of the plurality of posts. The dice are then electrically connected to a second set of the plurality of posts using wire bonding. An encapsulating material is placed over the dice and lead frame, with the connecting sheet keeping the encapsulating material on one side of the lead frame. The connecting sheet is then removed, leaving the posts as separate leads. The integrated circuits formed by the encapsulated dice and leads may be tested as a panel, before the integrated circuits are singulated.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: May 25, 2004
    Assignee: National Semiconductor Corporation
    Inventor: Shahram Mostafazadeh
  • Patent number: 6710246
    Abstract: A package, a method of making and a method of assembly of packages for semiconductor chips are disclosed. The package includes a die attach pad on which a semiconductor die is mounted. A lead is electrically connected to the semiconductor die which is encapsulated in packaging material. The lead is exposed at opposed sides of the package. Exposing the lead on both sides of the package allows the package to be stacked or assembled so that the leads of adjacent pairs of packages are in electrical contact. Making the semiconductor packages includes forming a piece of electrically conductive material into a die attach pad and at least one lead associated with the die attach pad. A semiconductor die is mounted on the die attach pad and an electrical connection is made between the semiconductor die and the lead. The package is formed by encapsulation with the lead exposed on opposite sides of the package.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: March 23, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Joseph O. Smith
  • Patent number: 6689640
    Abstract: An integrated circuit package with lead fingers with a footprint on the order of the integrated circuit footprint is provided. A lead frame may be made from a metal sheet, which may be stamped or etched. The lead frame provides a plurality of posts and a connecting sheet connecting the plurality of posts. Dice are adhesively mounted to the plurality of posts. The dice have a conductive side with a plurality of conducting pads where each conducting pad is electrically and mechanically connected to a post. An encapsulating material is placed over the dice and lead frame, with the connecting sheet keeping the encapsulating material on one side of the lead frame. Parts of the connecting sheet are then removed, electrically isolating the posts. The integrated circuit packages formed by the encapsulated dice and leads may be tested as a panel, before the integrated circuit packages are singulated.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: February 10, 2004
    Assignee: National Semiconductor Corporation
    Inventor: Shahram Mostafazadeh
  • Patent number: 6683368
    Abstract: A universal lead frame for mounting dice to form integrated circuit packages is provided. The lead frame may be made from a metal sheet, which may be stamped or etched. The lead frame provides a plurality of posts and a connecting sheet connecting the plurality of posts. Dice are adhesively mounted on to a first set of the plurality of posts. The dice are then electrically connected to a second set of the plurality of posts using wire bonding. An encapsulating material is placed over the dice and lead frame, with the connecting sheet keeping the encapsulating material on one side of the lead frame. The connecting sheet is then removed, leaving the posts as separate leads. The integrated circuits formed by the encapsulated dice and leads may be tested as a panel, before the integrated circuits are singulated.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: January 27, 2004
    Assignee: National Semiconductor Corporation
    Inventor: Shahram Mostafazadeh
  • Patent number: 6589814
    Abstract: A method for producing chip scale IC packages includes the step of mounting a lead frame panel on a temporary support fixture in order to provide support and protection during the manufacturing process. An embodiment of the temporary support fixture includes a sheet of sticky tape secured to a rigid frame. The rigid frame maintains tension in the sheet of sticky tape to provide a stable surface to which the lead frame panel can be affixed. Installation of IC chips and encapsulation in protective casings is performed as in conventional IC package manufacturing. If encapsulant material is to be dispensed over the IC chips, an encapsulant dam can be formed around the lead frame panel to contain the flow of encapsulant material. The temporary support fixture can be used in any IC package manufacturing process in which lead frames require supplemental support.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: July 8, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Joseph O. Smith
  • Patent number: 6468832
    Abstract: An encapsulated bumped die is provided. Singulated bumped dice are attached to a die attach panel. The die attach panel and dice are placed in a mold, where the bumps are partially flattened. A mold compound is then used to encapsulate the dice and panel. The mold compound is cured. The encapsulated dice are then singulated. The encapsulated dice may then be directly mounted on a substrate such as a PC board. The encapsulation provides added protection to the dice.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: October 22, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Shahram Mostafazadeh
  • Patent number: 6420212
    Abstract: An improved die cover is provided. The cover is formed from an enclosure with adhesive, which holds a die in the enclosure. The enclosure may be formed as part of a panel of enclosures. The panel of enclosures may be held together by ties. Conventional die attach machinery may be used to place adhesive and dice in the enclosures of the panel of enclosures. The dice may be tested as a panel, and then the enclosures may be singulated.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: July 16, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Shahram Mostafazadeh
  • Patent number: 6352878
    Abstract: A method and apparatus for forming a layer of underfill encapsulant on an integrated circuit located on a wafer are described. The integrated circuit has electrically conductive pads, a plurality of which have solder balls attached thereto. To reduce the occurrence of voids during formation of the underfill layer, the wafer is placed in a mold cavity which is evacuated prior to injection of the underfill encapsulant.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: March 5, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Joseph O. Smith
  • Patent number: 6245595
    Abstract: A method and apparatus for forming a layer of underfill encapsulant on an integrated circuit located on a wafer are described. As a flip chip, the integrated circuit has electrically conductive pads, most of which have a solder ball attached thereto. Most of the solder balls have been flattened in order to provide an enlarged solder wetting area. A layer of underfill encapsulant is injected onto the integrated circuit under pressure to form a layer of underfill encapsulant that is then pre-cured. The integrated circuit is mounted to a substrate and the substrate and the integrated circuit are electrically coupled by a solder reflow operation which also finally cures the underfill encapsulant.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: June 12, 2001
    Assignee: National Semiconductor Corporation
    Inventors: Luu Nguyen, Hem P. Takiar, Ethan Warner, Shahram Mostafazadeh, Joseph O. Smith
  • Patent number: 6184575
    Abstract: An ultra-thin composite package for integrated circuits including a metal base with a cavity to support a die with a molded plastic cap cooperating with the base to encapsulate the die. A lead frame having a thinned inner portion or lead tip areas may also be used to further reduce the package thickness. Package thicknesses of about 20 mils (0.5 mm) or less can be readily achieved using this structure combination.
    Type: Grant
    Filed: August 26, 1994
    Date of Patent: February 6, 2001
    Assignee: National Semiconductor Corporation
    Inventors: Satya Chillara, Shahram Mostafazadeh
  • Patent number: 6130473
    Abstract: A method for producing chip scale IC packages includes the step of mounting a lead frame panel on a temporary support fixture in order to provide support and protection during the manufacturing process. An embodiment of the temporary support fixture includes a sheet of sticky tape secured to a rigid frame. The rigid frame maintains tension in the sheet of sticky tape to provide a stable surface to which the lead frame panel can be affixed. Installation of IC chips and encapsulation in protective casings is performed as in conventional IC package manufacturing. If encapsulant material is to be dispensed over the IC chips, an encapsulant dam can be formed around the lead frame panel to contain the flow of encapsulant material. The temporary support fixture can be used in any IC package manufacturing process in which lead frames require supplemental support.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: October 10, 2000
    Assignee: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Joseph O. Smith
  • Patent number: 6117710
    Abstract: A molded plastic package incorporates a lead frame which includes a plurality of leads radially aligned around a central opening. A die is mounted in the central opening and is electrically connected to the leads by wire bonding. A molded plastic casing is formed over the die, wiring and lead frame to encapsulate the package. The lower surfaces of the die and lead frame are exposed through the package. A method for making the molded plastic package includes mounting the die and lead frame onto an adhesive tape, electrically connecting the die to the leads by wire bonding, forming a molded plastic casing over the die, wire bonding and lead frame, and then removing the adhesive tape to expose the lower surfaces of the die and the lead frame.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: September 12, 2000
    Assignee: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Joseph O. Smith