Patents by Inventor Shailendra Srinivas
Shailendra Srinivas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11853826Abstract: An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.Type: GrantFiled: July 19, 2022Date of Patent: December 26, 2023Assignee: Impinj, Inc.Inventors: John D. Hyde, Shailendra Srinivas, Jay Kuhn, Ronald A. Oliver, Harley Heinrich, Theron Stanford, Christopher J. Diorio
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Patent number: 11811415Abstract: A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.Type: GrantFiled: June 18, 2021Date of Patent: November 7, 2023Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Shailendra Srinivas, Joseph D. Cali, Steven E. Turner
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Publication number: 20220407524Abstract: A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Applicant: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Shailendra Srinivas, Joseph D. Cali, Steven E. Turner
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Patent number: 10929734Abstract: An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.Type: GrantFiled: October 10, 2019Date of Patent: February 23, 2021Assignee: Impinj, Inc.Inventors: John D. Hyde, Shailendra Srinivas, Jay Kuhn, Ronald A. Oliver, Harley Heinrich, Theron Stanford, Christopher J. Diorio
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Patent number: 10445535Abstract: An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.Type: GrantFiled: May 21, 2018Date of Patent: October 15, 2019Assignee: Impinj, Inc.Inventors: John D. Hyde, Shailendra Srinivas, Jay Kuhn, Ronald A. Oliver, Harley Heinrich, Theron Stanford, Christopher J. Diorio
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Patent number: 10002266Abstract: An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.Type: GrantFiled: August 6, 2015Date of Patent: June 19, 2018Assignee: Impinj, Inc.Inventors: John D. Hyde, Shailendra Srinivas, Jay Kuhn, Ronald A Oliver, Harley Heinrich, Theron Stanford, Christopher J. Diorio
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Patent number: 9875438Abstract: Embodiments are directed to a Radio Frequency Identification (RFID) integrated circuit (IC) having a first circuit block electrically coupled to first and second antenna contacts. The first antenna contact is disposed on a first surface of the IC and the second antenna contact is disposed on a second surface of the IC different from the first surface. The first and second antenna contacts are electrically disconnected from each other.Type: GrantFiled: February 4, 2016Date of Patent: January 23, 2018Assignee: IMPINJ, INC.Inventors: Christopher J. Diorio, Ronald L. Koepp, Harley K. Heinrich, Theron Stanford, Ronald A. Oliver, Shailendra Srinivas
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Patent number: 9489611Abstract: Embodiments are directed to a Radio Frequency Identification (RFID) integrated circuit (IC) having a first circuit block electrically coupled to first and second antenna contacts. The first antenna contact is disposed on a first surface of the IC and the second antenna contact is disposed on a second surface of the IC different from the first surface. The first and second antenna contacts are electrically disconnected from each other.Type: GrantFiled: February 4, 2016Date of Patent: November 8, 2016Assignee: IMPINJ INC.Inventors: Christopher J. Diorio, Ronald L. Koepp, Harley K. Heinrich, Theron Stanford, Ronald A. Oliver, Shailendra Srinivas
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Patent number: 9349090Abstract: A tuning circuit in an RFID tag may be used to match antenna and integrated circuit (IC) impedances to maximize the efficiency of IC power extraction from an incident RF wave. The tuning circuit, which requires less power to operate than the IC, adjusts a variable impedance to improve the impedance matching between the IC and the tag antenna and thereby increase the IC power extraction efficiency. The IC may begin operating according to a protocol when it extracts sufficient power from the RF wave or when an optimal impedance matching and power transfer is achieved.Type: GrantFiled: December 30, 2014Date of Patent: May 24, 2016Assignee: IMPINJ, INC.Inventors: Shailendra Srinivas, Jay Kuhn, Ronald A. Oliver, John D. Hyde, Christopher J. Diorio
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Publication number: 20150248604Abstract: Embodiments are directed to a Radio Frequency Identification (RFID) integrated circuit (IC) having a first circuit block electrically coupled to first and second antenna contacts. The first antenna contact is disposed on a first surface of the IC and the second antenna contact is disposed on a second surface of the IC different from the first surface. The first and second antenna contacts are electrically disconnected from each other.Type: ApplicationFiled: May 16, 2015Publication date: September 3, 2015Inventors: Christopher J. Diorio, Ronald L. Koepp, Harley K. Heinrich, Theron Stanford, Ronald A. Oliver, Shailendra Srinivas
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Publication number: 20150227832Abstract: Embodiments are directed to a Radio Frequency Identification (RFID) integrated circuit (IC) having a first circuit block electrically coupled to first and second antenna contacts. The first antenna contact is disposed on a first surface of the IC and the second antenna contact is disposed on a second surface of the IC different from the first surface. The first and second antenna contacts are electrically disconnected from each other.Type: ApplicationFiled: August 23, 2013Publication date: August 13, 2015Applicant: Impinj, Inc.Inventors: Christopher J. Diorio, Ronald L. Koepp, Harley K. Heinrich, Theron Stanford, Ronald A. Oliver, Shailendra Srinivas
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Patent number: 9053400Abstract: Embodiments are directed to a Radio Frequency Identification (RFID) integrated circuit (IC) having a first circuit block electrically coupled to first and second antenna contacts. The first antenna contact is disposed on a first surface of the IC and the second antenna contact is disposed on a second surface of the IC different from the first surface. The first and second antenna contacts are electrically disconnected from each other.Type: GrantFiled: August 23, 2013Date of Patent: June 9, 2015Assignee: Impinj, Inc.Inventors: Christopher J. Diorio, Ronald L. Koepp, Harley K. Heinrich, Theron Stanford, Ronald A. Oliver, Shailendra Srinivas
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Patent number: 8952792Abstract: A tuning circuit in an RFID tag may be used to match antenna and integrated circuit (IC) impedances to maximize the efficiency of IC power extraction from an incident RF wave. The tuning circuit, which requires less power to operate than the IC, adjusts a variable impedance to improve the impedance matching between the IC and the tag antenna and thereby increase the IC power extraction efficiency. The IC may begin operating according to a protocol when it extracts sufficient power from the RF wave or when an optimal impedance matching and power transfer is achieved.Type: GrantFiled: January 6, 2012Date of Patent: February 10, 2015Assignee: Impinj, Inc.Inventors: Shailendra Srinivas, Jay Kuhn, Ronald A. Oliver, John D. Hyde, Christopher J. Diorio
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Publication number: 20140073071Abstract: Embodiments are directed to a Radio Frequency Identification (RFID) integrated circuit (IC) having a first circuit block electrically coupled to first and second antenna contacts. The first antenna contact is disposed on a first surface of the IC and the second antenna contact is disposed on a second surface of the IC different from the first surface. The first and second antenna contacts are electrically disconnected from each other.Type: ApplicationFiled: August 23, 2013Publication date: March 13, 2014Inventors: Christopher J. Diorio, Ronald L. Koepp, Harley K. Heinrich, Theron Stanford, Ronald A. Oliver, Shailendra Srinivas
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Publication number: 20140070010Abstract: Embodiments are directed to a Radio Frequency Identification (RFID) integrated circuit (IC) having a first circuit block electrically coupled to first and second antenna contacts. The first antenna contact is disposed on a first surface of the IC and the second antenna contact is disposed on a second surface of the IC different from the first surface. The first and second antenna contacts are electrically disconnected from each other.Type: ApplicationFiled: August 23, 2013Publication date: March 13, 2014Applicant: Impinj, Inc.Inventors: Christopher J. Diorio, Ronald L. Koepp, Harley K. Heinrich, Theron Stanford, Ronald A. Oliver, Shailendra Srinivas
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Patent number: 8072329Abstract: The present disclosure provides examples of a voltage regulator for a Radio Frequency Identification tag circuit. The voltage regulator includes a pair of native transistors. A first native transistor is coupled to a reference voltage and biased to saturation. A resistive element coupled between the gate and the drain of the transistor ensures a sufficient voltage difference between the source and the drain of the first native transistor. The second native transistor, with a gate coupled to the gate of the first native transistor, outputs a regulated voltage.Type: GrantFiled: December 2, 2008Date of Patent: December 6, 2011Assignee: Impinj, Inc.Inventors: Shailendra Srinivas, Jay A. Kuhn
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Patent number: 7573749Abstract: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.Type: GrantFiled: March 29, 2007Date of Patent: August 11, 2009Assignee: Virage Logic CorporationInventors: Christopher J. Diorio, Chad A. Lindhorst, Shailendra Srinivas, Alberto Pesavento, Troy N. Gilliland
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Publication number: 20070171724Abstract: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.Type: ApplicationFiled: March 29, 2007Publication date: July 26, 2007Applicant: Impinj, Inc.Inventors: Christopher Diorio, Chad Lindhorst, Shailendra Srinivas, Alberto Pesavento, Troy Gilliland
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Patent number: 7212446Abstract: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.Type: GrantFiled: April 21, 2004Date of Patent: May 1, 2007Assignee: Impinj, Inc.Inventors: Christopher J. Diorio, Chad A. Lindhorst, Shailendra Srinivas, Alberto Pesavento, Troy N. Gilliland
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Publication number: 20050030827Abstract: A single-poly PMOS nonvolatile memory (NVM) cell and a method of programming, erasing and reading such a cell are implemented using a single-poly PMOS NVM cell which includes a floating gate injection transistor, a select switch, and a tunneling capacitor having one plate in common with the floating gate of the injection transistor. Methods of altering the number of electrons on the floating gate of the single-poly PMOS NVM cell are used which, with appropriate biasing of the components permit the power terminals of the cell to have appropriate voltages applied to thereby avoid stuck bits and induce hot electrons onto the floating gate of the NVM cell.Type: ApplicationFiled: September 7, 2004Publication date: February 10, 2005Inventors: Troy Gilliland, Chad Lindhorst, Christopher Diorio, Todd Humes, Shailendra Srinivas