Abstract: Provided are transaminase mutants and uses thereof. The transaminase mutant is obtained by one or more amino acid mutations occurring in SEQ ID NO: 2 or is a mutant with a conserved amino acid mutation obtained by taking the sequence SEQ ID NO: 1 of a wild-type CvTA transaminase as a reference. Compared with wild-type transaminases, the catalytic activity of the mutant is improved to different degrees, so that the production efficiency of chiral amine compound synthesis may be improved.

Abstract: The present disclosure provides a preparation method of an easy-to-cook whole grain based on microwave-induced cracking, and belongs to the technical field of food processing. In the present disclosure, the preparation method of an easy-to-cook whole grain includes the following steps: subjecting a whole grain to a heat-moisture treatment, and conducting short-time microwave-induced cracking, tempering, and cooling to obtain the easy-to-cook whole grain. The easy-to-cook whole grain obtained by the preparation method of the present disclosure has a complete grain, a slightly-expanded volume, and fine cracks on its surface. Compared with unprocessed whole grains, the easy-to-cook whole grain has a water absorption increased from 1.35 times to 1.9 times an original weight of the unprocessed whole grains during rice steaming.

Abstract: The present invention discloses methods and systems for scheduling and distributing power for electric vehicle chargers, through enabling and disabling a plurality of relays at a system. One of the criteria to allow an authenticated user to use an electric vehicle charger is whether there is enough electricity capacity. When the user is allowed to use a scheduled electric vehicle charger, its location is then sent to the user. Alert messages can be generated if charging does not begin within a first time limit and the cancellation of a reservation will take place if the second time limit is reached.

Abstract: The present disclosure provides an open-air circulating pool for simulating ecological damage, and belongs to the technical field of simulation tests of ecological environment impact. The open-air circulating pool is provided with a set of devices for simulating natural ecological environments of different water quality and sediments, as well as changes in water bodies caused by a sea occupation project, discharge of a typical pollution source and a sudden leakage accident, so as to observe changing trends of an aquatic organism and an environmental element, and qualitatively and quantitatively determine a law of causality of damage. The set of devices includes an open-air wave-flow circulating pool, an additive injection apparatus and an ecological indicator sampling and detection apparatus.

Abstract: The present disclosure provides an open-air circulating pool for simulating ecological damage, and belongs to the technical field of simulation tests of ecological environment impact. The open-air circulating pool is provided with a set of devices for simulating natural ecological environments of different water quality and sediments, as well as changes in water bodies caused by a sea occupation project, discharge of a typical pollution source and a sudden leakage accident, so as to observe changing trends of an aquatic organism and an environmental element, and qualitatively and quantitatively determine a law of causality of damage. The set of devices includes an open-air wave-flow circulating pool, an additive injection apparatus and an ecological indicator sampling and detection apparatus.

Abstract: Non-volatile memory and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate; forming a first conductive layer on the base substrate; forming an interlayer dielectric layer on the first conductive layer; forming a plurality of through holes exposing the first conductive layer in the interlayer dielectric layer; forming a catalyst layer on at least one of sidewall surfaces and bottom surfaces of the through holes; forming a carbon nanotube layer in the through holes by a catalytic chemical vapor deposition process; and forming a second conductive layer on the carbon nanotube layer and a portion of the interlayer dielectric layer.

Abstract: A FinFET device and fabrication method thereof is provided. The method includes: providing a semiconductor substrate and fins. Each fin includes a first sidewall region and a second sidewall region. An interlayer dielectric layer is formed on the semiconductor substrate and on the fins, with openings. Then a target work function layer is formed on sidewalls and on a bottom of each opening. The target work function layer includes a first target region covering the first sidewall region, a second target region covering the second sidewall region, and a third portion on the top surface of each fin. The second target region and the third portion of the target work function layer is doped with modification ions; and has a second effective work function value greater than a first effective work function value of the first target region of the target work function layer.

Abstract: A semiconductor structure and a method for fabricating a semiconductor structure are provided. The method includes forming one or more fins on a substrate, wherein each fin includes a first sidewall and a second sidewall opposing each other. The method also includes forming a sacrificial layer over the fin. Further, the method also includes performing a first ion implantation process on the first sidewall and a top of the fin, and performing a second ion implantation process on the second sidewall and the top of the fin.

Abstract: A FinFET device and fabrication method thereof is provided. The method includes: providing a semiconductor substrate and fins. Each fin includes a first sidewall region and a second sidewall region. An interlayer dielectric layer is formed on the semiconductor substrate and on the fins, with openings. Then a target work function layer is formed on sidewalls and on a bottom of each opening. The target work function layer includes a first target region covering the first sidewall region, a second target region covering the second sidewall region, and a third portion on the top surface of each fin. The second target region and the third portion of the target work function layer is doped with modification ions; and has a second effective work function value greater than a first effective work function value of the first target region of the target work function layer.

Abstract: A semiconductor structure and a method for fabricating a semiconductor structure are provided. The method includes forming one or more fins on a substrate, wherein each fin includes a first sidewall and a second sidewall opposing each other. The method also includes forming a sacrificial layer over the fin. Further, the method also includes performing a first ion implantation process on the first sidewall and a top of the fin, and performing a second ion implantation process on the second sidewall and the top of the fin.

Abstract: An improved pseudomorphic high electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) integrated epitaxial structure, in which the structure comprises a substrate, a pHEMT structure, an etching-stop spacer layer, and an HBT structure. The pHEMT structure comprises a buffer layer, a bottom barrier layer, a first channel spacer layer, a channel layer, a second channel spacer layer, a Schottky spacer layer, a Schottky donor layer, a Schottky barrier layer, an etching-stop layer, and at least one cap layer. By introducing the first channel spacer layer and the second channel spacer layer to reduce the density of the dislocations and to reduce the compressive strain in the pseudomorphic channel layer.

Abstract: An improved pseudomorphic high electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) integrated epitaxial structure and the fabrication method thereof, in which the structure comprises a substrate, a pHEMT structure, an etching-stop spacer layer, and an HBT structure. The pHEMT's structure comprises a buffer layer, a barrier layer, a first channel spacer layer, a channel layer, a second channel spacer layer, a Schottky barrier layer, an etching-stop layer, and at least one cap layer. The fabrication method of an HBT and a pHEMT are also included.

Abstract: A flash memory cell includes a substrate having a surface region and a flash memory cell structure on the surface region. The flash memory cell structure includes a gate dielectric layer on the surface region, a select gate on the gate dielectric layer, a cap oxide layer on the select gate, an oxide spacer on a first edge of the select gate, a tunnel oxide layer on a first region and on a second region of the surface region. The second region is an active region. The flash memory cell structure further includes a poly spacer on the first edge of the oxide spacer and a portion of the tunnel oxide layer on the first region, an ONO layer on at least the poly spacer and a control gate layer on the ONO layer.

Abstract: A polysilicon spacer as a floating gate of a Flash memory device. An advantage of such spacer structure is to reduce a cell size, which is desirable for state-of-the-art Flash memory technology. In a preferred embodiment, the floating gate can be self-aligned to a nearby and/or within a vicinity of the select gate of the cell select transistor. In a preferred embodiment, the present invention preserves a tunnel oxide layer after the removal, using dry etching, a polysilicon spacer structure on the drain side of the select transistor gate. More preferably, the present method provides for a certain amount of tunnel oxide to remain so as to prevent the active silicon area in the drain region of the memory cell from being etched by the dry etching gas.

Abstract: A polysilicon spacer as a floating gate of a Flash memory device. An advantage of such spacer structure is to reduce a cell size, which is desirable for state-of-the-art Flash memory technology. In a preferred embodiment, the floating gate can be self-aligned to a nearby and/or within a vicinity of the select gate of the cell select transistor. In a preferred embodiment, the present invention preserves a tunnel oxide layer after the removal, using dry etching, a polysilicon spacer structure on the drain side of the select transistor gate. More preferably, the present method provides for a certain amount of tunnel oxide to remain so as to prevent the active silicon area in the drain region of the memory cell from being etched by the dry etching gas.

Abstract: A method for fabricating an integrated circuit device, e.g., CMOS image sensor. The method includes providing a semiconductor substrate, which has a first device region and a second device region. The method forms a gate polysilicon layer overlying the first and second device regions. The method forms a silicide layer overlying the gate polysilicon layer. The method patterns the silicide layer and gate polysilicon layer to form a first silicided gate structure in the first device region and a second silicided gate structure in the second device region. The method also includes forming a blocking layer overlying the second device region. The method forms a silicide material overlying a first source region and a first drain region associated with the first silicided gate structure, and maintaining a second source region and a second drain region associated with the second silicided gate structure free from any silicide using the blocking layer.

Abstract: An oxidized low density lipoprotein sensing device for a gallium nitride process is a GaN HEMT device including: a gateless AlGaN/GaN sensing transistor device, a testing window, a source, a drain, two metal connecting wires and a passivation layer. The gateless AlGaN/GaN sensing transistor device has an epitaxial wafer structure including a GaN layer and an aluminum gallium nitride layer. The testing window is disposed on the epitaxial wafer structure. The metal connecting wire is disposed on a source and a drain. The passivation layer is covered onto a surface of the sensing device except the testing window. A built-in piezoelectric field is created by the properties of FET and the polarization effect of AlGaN/GaN to achieve the effect of sensing the level of oxidizing proteins in human body quickly, accurately and easily.