Patents by Inventor Shan Hong

Shan Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7759710
    Abstract: An oxidized low density lipoprotein sensing device for a gallium nitride process is a GaN HEMT device including: a gateless AlGaN/GaN sensing transistor device, a testing window, a source, a drain, two metal connecting wires and a passivation layer. The gateless AlGaN/GaN sensing transistor device has an epitaxial wafer structure including a GaN layer and an aluminum gallium nitride layer. The testing window is disposed on the epitaxial wafer structure. The metal connecting wire is disposed on a source and a drain. The passivation layer is covered onto a surface of the sensing device except the testing window. A built-in piezoelectric field is created by the properties of FET and the polarization effect of AlGaN/GaN to achieve the effect of sensing the level of oxidizing proteins in human body quickly, accurately and easily.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: July 20, 2010
    Assignee: Chang Gung University
    Inventors: Hsien-Chin Chiu, Chao-Sung Lai, Bing-Shan Hong, Chao-Wei Lin, S. E. Chow, Ray-Ming Lin, Yung-Hsiang Lin, Hsin-Shun Huang
  • Publication number: 20080145990
    Abstract: A method for fabricating an integrated circuit device, e.g., CMOS image sensor. The method includes providing a semiconductor substrate, which has a first device region and a second device region. The method forms a gate polysilicon layer overlying the first and second device regions. The method forms a silicide layer overlying the gate polysilicon layer. The method patterns the silicide layer and gate polysilicon layer to form a first silicided gate structure in the first device region and a second silicided gate structure in the second device region. The method also includes forming a blocking layer overlying the second device region. The method forms a silicide material overlying a first source region and a first drain region associated with the first silicided gate structure, and maintaining a second source region and a second drain region associated with the second silicided gate structure free from any silicide using the blocking layer.
    Type: Application
    Filed: December 23, 2006
    Publication date: June 19, 2008
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Zhong Shan Hong, Xian Yong Pu