Abstract: The invention provides an aircraft attitude tracking control method, system and computer equipment, which belongs to the field of aircraft attitude control, comprising: obtaining aircraft operating parameters and establishing a kinematic model of the attitude tracking error of the aircraft. A specified time performance constraint function and attitude error boundary based on the hyperbolic cosecant composite function are then constructed. A constrained attitude error conversion function and its inverse function are utilized to obtain an unconstrained attitude tracking conversion error. Virtual control instructions are solved in kinematics using a sigmoid tracking differentiator to obtain a numerical derivative. The control moment in the dynamics is solved and the complete form of the attitude tracking algorithm is given for the aircraft attitude tracking system. This method provides a computationally efficient means of controlling aircraft to ensure that error convergence is achieved within a preset time.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: The invention provides an aircraft attitude tracking control method, system and computer equipment, which belongs to the field of aircraft attitude control, comprising: obtaining aircraft operating parameters and establishing a kinematic model of the attitude tracking error of the aircraft. A specified time performance constraint function and attitude error boundary based on the hyperbolic cosecant composite function are then constructed. A constrained attitude error conversion function and its inverse function are utilized to obtain an unconstrained attitude tracking conversion error. Virtual control instructions are solved in kinematics using a sigmoid tracking differentiator to obtain a numerical derivative. The control moment in the dynamics is solved and the complete form of the attitude tracking algorithm is given for the aircraft attitude tracking system. This method provides a computationally efficient means of controlling aircraft to ensure that error convergence is achieved within a preset time.

Abstract: A thinner composition and a method for substrate processing are provided. The thinner composition includes a solvent (A) and a fluorine-containing additive (B). The fluorine-containing additive (B) includes a compound represented by following Formula (B-1), a polymer represented by following Formula (B-2), a polymer represented by following Formula (B-3), or a combination thereof. In Formula (B-1), Formula (B-2), and Formula (B-3), the definition of X1 to X10, R1 to R13, m, T, j, k, p, and q are the same as defined in the specification.

Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.

Abstract: A method for hepatocellular carcinoma (HCC) subtype classification and treatment may include identifying, for a liver epithelial cell lineage, one or more features associated with the liver epithelial cell lineage. The one or more features may be designated as representative of a molecular subtype associated with hepatocellular carcinoma (HCC) such as, for example, a cholangio-like subtype, a hepatocyte-like subtype, or a progenitor-like subtype. A patient may be determined to exhibit the molecular subtype if these features are detected within the tumor sample of the patient. Moreover, treatment for the patient may be determined based on the molecular subtype exhibited by the patient. For example, treatment for the patient may include additional therapies, such as an GPC3/CD3 bi-specific antibody, to overcome subtype-specific resistance to combination immunotherapy associated with the progenitor-like subtype. Related systems and computer program products are also provided.

Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor structure. The method includes forming an active region over a substrate, forming a dummy gate layer over the active region, forming a hard mask layer over the dummy gate layer, forming a patterned photoresist over the hard mask layer, and performing an etching process to the hard mask layer and the dummy gate layer using the patterned photoresist, thereby forming patterned hard mask structures and patterned dummy gate structures. The patterned hard mask structures are formed with an uneven profile having a protruding portion. The protruding portion of each of the patterned hard mask structures has a first width, wherein each of the patterned dummy gate structures has a second width, and the first width is greater than the second width.

Abstract: A apparatus, method, system and medium are provided. The apparatus includes: a buffer chain, including N first buffers connected end to end, N first AND gates with one input connected to a pulse signal and the other input connected to an output of a corresponding first buffer, and N flip-flops coupled with outputs of respective first AND gates; a path time delay adjustment circuit, with an input receiving a pulse signal, and an output connected to an input terminal of the first buffer; a control apparatus, controlling the time delay produced by the adjustment circuit to be reduced by at least one step from a preset time delay during each adjustment until an output of a Pth flip-flop flips; a measuring device measuring the pulse signal's width according to an output of each flip-flop, the time delay of each first buffer and the time delay of the adjustment circuit.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A bus anomaly detecting method, processing method, apparatus, system, device, and medium. The bus anomaly detecting method includes: at an interface for connecting a bus, activating a detection state in response to an access initiating apparatus sending an access request to an access receiving apparatus so as to, in the detection state, perform anomaly detection on response signal fed back by the access receiving apparatus for each access request, and block an interruption signal sent by the access initiating apparatus; in response to a response signal corresponding to an access request having an anomaly, terminating the detection state, recording bus anomaly information, and sending an interruption signal; and in a case where the response signal corresponding to each access request sent by the access initiating apparatus is received and has no anomaly, terminating the detection state to stop blocking the interruption signal sent by the access initiating apparatus.

Abstract: A data conversion method and apparatus, an electronic device and a storage medium for converting dimensions of a first data combination. The data conversion method includes: reading n elements in the first data combination according to a first-dimension direction to obtain a first processing group, a first element to an n-th element in the first processing group are arranged according to the first-dimension direction, and n is a positive integer; performing a transpose on the first dimension and the third dimension of the first processing group to obtain a second processing group, a first element to an n-th element in the second processing group are arranged in a third-dimension direction; and writing the first element to the n-th element in the second processing group to a first storage.

Abstract: A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.

Abstract: A semiconductor structure that includes a first semiconductor fin and a second semiconductor fin disposed over a substrate and adjacent to each other, a metal gate stack disposed over the substrate, and source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack. The metal gate stack includes a first region disposed over the first semiconductor fin, a second region disposed over the second semiconductor fin, and a third region connecting the first region to the second region in a continuous profile, where the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length.

Abstract: Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes forming a semiconductor fin over a substrate, forming an integral dielectric layer over the substrate, wherein the dielectric layer includes a first portion extending along a sidewall surface of the semiconductor fin and a second portion disposed over the semiconductor fin, a thickness of the second portion of the dielectric layer is greater than a thickness of the first portion of the dielectric layer, forming a dummy gate electrode layer over the substrate, patterning the dielectric layer and the dummy gate electrode layer to form a dummy gate structure over a channel region of the semiconductor fin, forming source/drain features coupled to the channel region of the semiconductor fin and adjacent to the dummy gate structure, and replacing the dummy gate structure with a gate stack.

Abstract: A method and a system for performing a matrix multiplication operator using a unit supporting convolution operator operation, an electronic device, and a non-transitory storage medium are provided. The method includes: transforming a first matrix of the matrix multiplication operator to an input data matrix of a convolution operator; transforming a second matrix of the matrix multiplication operator to a weight matrix of the convolution operator, matrix multiplication being performed on the first matrix and the second matrix; and performing a convolution operation on the input data matrix and the weight matrix, which are obtained through transforming, of the convolution operator using the unit supporting convolution operator operation to obtain an operation result of the matrix multiplication operator.

Abstract: A chip, a chip system, and a timestamp synchronization method. The chip is configured to be in communication connection to another chip, and includes a signal generating module, a first signal response module and a first delay module. The signal generating module is configured to generate a synchronization request signal and transmit the synchronization request signal to the first signal response module and the another chip, so that the another chip records a second timestamp of the another chip in response to receiving the synchronization request signal. The first delay module is configured to perform delay processing on the synchronization request signal to obtain a delayed synchronization request signal. The first signal response module is configured to record a first timestamp of the chip in response to receiving the delayed synchronization request signal, wherein the first timestamp and the second timestamp are used for performing a timestamp synchronization operation.

Abstract: A computing apparatus and method, an electronic device and a storage medium are provided. The computing apparatus includes: a preprocessing module configured to receive N pairs of input parameters, and perform format conversion on each pair of input parameters according to the precision type of the N pairs of input parameters, and obtain N pairs of processed input parameters; and a calculation module configured to respectively compute a product of exponents and mantissas of each pair of processed input parameters, and obtain an output result based on the product of exponents and mantissas of each pair of processed input parameters. The computing apparatus supports multiply-accumulate computation of a plurality of floating-point types. The computing apparatus can multiplex the multiplication computation of the mantissa and make the computing apparatus support multiply-accumulate computations in a plurality of precision formats at the cost of lower area and power consumption.

Abstract: Embodiments of the present disclosure provide a device and a method for monitoring power supply voltage of an electronic circuit.

Abstract: Embodiments of the present disclosure provide an apparatus and a method for generating a circuit clock signal. The apparatus comprises: a clock buffer configured to buffer an original clock signal to obtain a buffered clock signal; a clock delay unit configured to delay the original clock signal to obtain a plurality of delayed clock signals, the plurality of delayed clock signals being respectively delayed by different amounts of time relative to the original clock signal; a broadened clock generator configured to generate a broadened clock signal based on the original clock signal and the plurality of delayed clock signals, the frequency of the broadened clock signal being lower than that of the original clock signal; and a clock selector configured to select one of the buffered clock signal and the broadened clock signal as the circuit clock signal based on a selection signal.

Abstract: A semiconductor structure that includes a first semiconductor fin and a second semiconductor fin disposed over a substrate and adjacent to each other, a metal gate stack disposed over the substrate, and source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack. The metal gate stack includes a first region disposed over the first semiconductor fin, a second region disposed over the second semiconductor fin, and a third region connecting the first region to the second region in a continuous profile, where the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length.