Abstract: A pharmaceutical composition, a preparation and a use for treating oral mucosal wounds. The pharmaceutical composition includes a glutamine, s mucoadhesive polymer, and a slow-release polymer. The mucoadhesive polymer is charged polymer. The slow-release polymer is uncharged polymer. Based on the total weight of the pharmaceutical composition, the content of glutamine is 5% by weight to 75% by weight, the content of mucoadhesive polymer is 20% by weight to 70% by weight, and the content of slow-release polymer is 20% by weight to 70% by weight.

Abstract: Disclosed is a catheter device including a proximal tube having a first part of a first lumen; a distal tube having a second part of the first lumen; a second lumen connecting the proximal tube and the distal tube; wherein the connection comprise an area of discontinuity between the first part and second part; wherein the area of discontinuity comprises a support element configured to resist axial movement of the distal tube relative to the proximal tube and vice versa; and wherein the second lumen is arranged to activate or cause at least one obstruction element to restrict the flow of urine from the proximal tube to the area of discontinuity and to restrict the flow of urine from the area of discontinuity to the distal tube.

Abstract: Polyvalent, primary isolate nucleic acid compositions for inducing an immune response against HIV are disclosed. The compositions and methods described herein are for the use of a nucleic acid composition that encodes one or more different HIV envelope glycoproteins. The synthetic, codon-optimized DNAs encoding one or more HIV proteins are a combination of different nucleic acids, such as DNA plasmids, generated from primary isolate DNA of different HIV major group genetic clades and/or different proteins. HIV polypeptide compositions for inducing an immune response against HIV are also disclosed. Methods for using the polypeptide compositions before, at the same time as, and/or after administration of the DNA compositions are provided.

Abstract: A device and method for evaluating long-term operation of a transformer oil pump. An inlet of an oil pump is connected to an outlet of an oil tank through an oil pipe, and an outlet of the oil pump is connected to an inlet of the oil tank through an oil pipe. A pressure gauge is provided on the oil pipe to the inlet and the outlet of the oil pump, respectively. An ultra-high-frequency (UHF) sensor is provided on an inner wall of an oil pipe close to the oil pump. A pressure difference between the oil pipes to the inlet and to the outlet of the oil pump is monitored. A three-phase unbalanced current of a stator winding is monitored. The vibration of the oil pump is monitored. The rotor-to-stator rub is monitored. Based on the above inspection, a long-term health status of the oil pump is determined.

Abstract: A mouse pad includes a mat part having a fixation portion and a 3D decorative object removably fixed on the fixation portion.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: An adhesive promoter, an organic silicon encapsulant composition, and an organic silicon encapsulant are provided. The adhesive promoter used for the organic silicon encapsulant is formed from a borosiloxane polymer represented by a general formula of: (R1R22SiO1/2)x(R2R3SiO2/2)y(R3SiO3/2)z(SiO4/2)i(BO(3-k)/2)j(OR4)k. R1 is a hydrogen atom or a C2-C6 alkenyl group. R2 and R4 are respectively a C1-C6 alkyl group. R3 is a C6-C12 aromatic group. In the general formula, x, y, z, i, j, and k represent a molar ratio. In the general formula, x, y, z, i, and j are a non-negative number smaller than or equal to 1, and k is a positive number ?3. A sum of x, y, z, and i is 1, and x is larger than 0.

Abstract: A semiconductor structure that includes a first semiconductor fin and a second semiconductor fin disposed over a substrate and adjacent to each other, a metal gate stack disposed over the substrate, and source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack. The metal gate stack includes a first region disposed over the first semiconductor fin, a second region disposed over the second semiconductor fin, and a third region connecting the first region to the second region in a continuous profile, where the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length.

Abstract: A semiconductor structure includes a fin extending from a substrate and oriented lengthwise in a first direction, where the fin includes a stack of semiconductor layers, an isolation feature disposed over the substrate and oriented lengthwise in a second direction perpendicular to the first direction, where the isolation feature is disposed adjacent to the fin, and a metal gate structure having a top portion disposed over the stack of semiconductor layers and a bottom portion interleaved with the stack of semiconductor layers. Furthermore, a sidewall of the bottom portion of the metal gate structure is defined by a sidewall of the isolation feature, and the top portion of the metal gate structure laterally extends over a top surface of the isolation feature.

Abstract: A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data one by one; and write the n intermediate data and a sign signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the sign signal; different values of the sign signal respectively represent different processing processes of the first data processing, and n is a positive integer.

Abstract: A apparatus, method, system and medium are provided. The apparatus includes: a buffer chain, including N first buffers connected end to end, N first AND gates with one input connected to a pulse signal and the other input connected to an output of a corresponding first buffer, and N flip-flops coupled with outputs of respective first AND gates; a path time delay adjustment circuit, with an input receiving a pulse signal, and an output connected to an input terminal of the first buffer; a control apparatus, controlling the time delay produced by the adjustment circuit to be reduced by at least one step from a preset time delay during each adjustment until an output of a Pth flip-flop flips; a measuring device measuring the pulse signal's width according to an output of each flip-flop, the time delay of each first buffer and the time delay of the adjustment circuit.

Abstract: A method for manufacturing a semiconductor structure includes forming a fin over a substrate, wherein the fin includes first semiconductor layers and second semiconductor layers alternating stacked. The method also includes forming an isolation feature around the fin, forming a dielectric feature over the isolation feature, forming a cap layer over the fin and the dielectric feature, oxidizing the cap layer to form an oxidized cap layer, forming source/drain features passing through the cap layer and in the fin, removing the second semiconductor layers in the fin to form nanostructures, and forming a gate structure wrapping around the nanostructures.

Abstract: A voltage detection circuit and method for an integrated circuit, and an integrated circuit are provided. The voltage detection circuit includes: a first current source, a first branch and a second branch. A current outputted by the first current source is allocated to the first branch and the second branch. The first branch includes a first voltage control current component and a first load connected in series. The second branch includes a current signal detection component and a second load connected in series. A voltage signal to be detected is inputted to a control signal input terminal of the first voltage control current component. The current signal detection component is configured to output, in real time, a preset signal characterizing a second current flowing through the second branch, to determine change of the voltage signal to be detected based on the preset signal.

Abstract: Disclosed are a temperature measurement circuit and method. The circuit includes a first temperature sensing circuit, a second temperature sensing circuit and a data processing unit. The first temperature sensing circuit is configured to generate a first measurement signal for characterizing a temperature based on an inputted first current signal, a magnitude of the first current signal being correlated to temperature. The second temperature sensing circuit is configured to generate a second measurement signal for characterizing the temperature based on an inputted second current signal, the second current signal being independent of temperature. The data processing unit is configured to determine a current temperature based on a first characteristic parameter corresponding to the first measurement signal and a second characteristic parameter corresponding to the second measurement signal.

Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.

Abstract: An integrated circuit, and a data processing device and method are provided. The integrated circuit includes a processor circuit and an accelerator circuit. The processor circuit includes a processor, a first data storage section, and a first data input/output interface. The accelerator circuit includes an accelerator and a second data input/output interface. The second data input/output interface is electrically connected to the first data input/output interface, so that the accelerator circuit can perform information interaction with the first data storage section.

Abstract: The application provides an apparatus, a system, a detector and a method. The apparatus includes: a power supply voltage detector, including: N buffers, an input terminal of a first buffer being connected to a clock signal, output terminals of other buffers being connected to the input terminal of an adjacent buffer; N latch chains, each of which includes M latches, a clock input terminal of each latch being connected to a clock signal, a D terminal of a first latch of each latch chain being connected to the output terminal of a corresponding buffer, Q terminals of other latches being connected to the D terminal of an adjacent latch, M and N being positive integers, the D terminal of each latch being connected to an area where a power supply voltage is to be detected; and a voltage regulation module connected to the Q terminal of each latch.

Abstract: A circuit module for performing matrix multiplication and a method for performing matrix multiplication are provided. The circuit module includes a row-column calculation unit for performing a row-column multiplication calculation. The row-column calculation unit includes a multiplication unit and an addition unit. The multiplication unit is configured to perform a multiplication calculation based on a row matrix element of a first matrix and a column matrix element of a second matrix, and receive at least one electrical signal sequentially inputted in multiple predetermined timing sequences via an input end of the multiplication unit. The electrical signal represents the row matrix element of the first matrix. The addition unit is configured to accumulate a product, obtained by the multiplication unit based on the inputted electrical signal, to perform the row-column multiplication calculation.

Abstract: A matrix multiplication circuit module and a matrix multiplication method are provided by the embodiments of the present disclosure. The circuit module includes one or more row-column calculation units for realizing row-column multiplication calculation. Each of the row-column calculation units comprises one or more multiplying units and an adding unit. Each of the one or more multiplying unit has an output end connected to an input end of the adding unit. Each of the multiplying units comprises an electrical signal regulating subunit and a load. The electrical signal regulating subunit is configured to regulate a magnitude of an input electrical signal. A multiplication operation is performed by the electrical signal regulating subunit and the load in response to an electrical signal inputted to the multiplying unit. The load has a fixed load value.

Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.