Abstract: A chip, a chip system, and a timestamp synchronization method. The chip is configured to be in communication connection to another chip, and includes a signal generating module, a first signal response module and a first delay module. The signal generating module is configured to generate a synchronization request signal and transmit the synchronization request signal to the first signal response module and the another chip, so that the another chip records a second timestamp of the another chip in response to receiving the synchronization request signal. The first delay module is configured to perform delay processing on the synchronization request signal to obtain a delayed synchronization request signal. The first signal response module is configured to record a first timestamp of the chip in response to receiving the delayed synchronization request signal, wherein the first timestamp and the second timestamp are used for performing a timestamp synchronization operation.

Abstract: Embodiments of the present disclosure provide a device and a method for monitoring power supply voltage of an electronic circuit.

Abstract: Embodiments of the present disclosure provide an apparatus and a method for generating a circuit clock signal. The apparatus comprises: a clock buffer configured to buffer an original clock signal to obtain a buffered clock signal; a clock delay unit configured to delay the original clock signal to obtain a plurality of delayed clock signals, the plurality of delayed clock signals being respectively delayed by different amounts of time relative to the original clock signal; a broadened clock generator configured to generate a broadened clock signal based on the original clock signal and the plurality of delayed clock signals, the frequency of the broadened clock signal being lower than that of the original clock signal; and a clock selector configured to select one of the buffered clock signal and the broadened clock signal as the circuit clock signal based on a selection signal.

Abstract: A semiconductor structure that includes a first semiconductor fin and a second semiconductor fin disposed over a substrate and adjacent to each other, a metal gate stack disposed over the substrate, and source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack. The metal gate stack includes a first region disposed over the first semiconductor fin, a second region disposed over the second semiconductor fin, and a third region connecting the first region to the second region in a continuous profile, where the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length.

Abstract: A voltage detection circuit and method for an integrated circuit, and an integrated circuit are provided. The voltage detection circuit includes: a first current source, a first branch and a second branch. A current outputted by the first current source is allocated to the first branch and the second branch. The first branch includes a first voltage control current component and a first load connected in series. The second branch includes a current signal detection component and a second load connected in series. A voltage signal to be detected is inputted to a control signal input terminal of the first voltage control current component. The current signal detection component is configured to output, in real time, a preset signal characterizing a second current flowing through the second branch, to determine change of the voltage signal to be detected based on the preset signal.

Abstract: A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data one by one; and write the n intermediate data and a sign signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the sign signal; different values of the sign signal respectively represent different processing processes of the first data processing, and n is a positive integer.

Abstract: A method for recognizing a video action includes determining an action category and action positioning information of a current video frame based on the current video frame and at least one forward video frame; and determining action content of a video based on the action category and the action positioning information of the current video frame.

Abstract: A temperature sensor system in a chip and the chip are provided. The temperature sensor system in the chip includes the first temperature sensing unit and a control unit. The first temperature sensing unit senses a temperature by using a back-end-of-line metal structure formed in a back-end-of-line process of the chip to output a temperature sensing electrical signal; and the control unit is coupled with the first temperature sensing unit, and processes the temperature sensing electrical signal output by the first temperature sensing unit to output a measurement result.

Abstract: Embodiments of the present disclosure provide a display substrate, a fabrication method thereof, a display panel and a display device. The display substrate includes: a driver circuit board including a plurality of functional film layers; and a planarization layer on the driver circuit board. The display substrate further includes a display region and a first edge region. The first edge region surrounds a periphery of the display region. Part of the functional film layers extends from the display region to the first edge region. The planarization layer extends from the display region to an area of the first edge region that borders the display region. The display substrate includes a flow guide structure disposed on a side of the planarization layer facing away from the driver circuit board, and on at least one side of a boundary of the planarization layer.

Abstract: An integrated circuit, and a data processing device and method are provided. The integrated circuit includes a processor circuit and an accelerator circuit. The processor circuit includes a processor, a first data storage section, and a first data input/output interface. The accelerator circuit includes an accelerator and a second data input/output interface. The second data input/output interface is electrically connected to the first data input/output interface, so that the accelerator circuit can perform information interaction with the first data storage section.

Abstract: A board game set includes a mat part, at least one first coil disposed in the mat part, and at least one game piece comprising a main body, a light-emitting unit, and an second coil, the light-emitting unit is disposed at the main body, the second coil is disposed in the main body and electrically coupled to the light-emitting unit, when the second coil approaches the at least one first coil, magnetic induction is generated and converted into electricity to be provided to activate the light-emitting unit.

Abstract: An X-ray tube bearing assembly may include a bearing housing including an accommodating cavity; and a bearing core accommodated in the accommodating cavity. The bearing housing may include first and second portions. The second portion surrounds and forms a portion of the accommodating cavity to accommodate the bearing core. The first portion extends out of the second portion and surrounds and forms another portion of the accommodating cavity, and the other portion of the accommodating cavity forms an accommodating hollow cavity. The first portion may have a different structural rigidity to that of the second portion.

Abstract: The present invention provides a Solanum lycopersicum seed oil freeze-dried powder with whitening efficacy, a composition, and a preparation method and application thereof. The Solanum lycopersicum seed oil freeze-dried powder has significant whitening efficacy. If the Solanum lycopersicum seed oil freeze-dried powder is used in combination with a lemon verbena extract with a dose ratio of 3:1, the whitening effect is synergistic with the lemon verbena extract. The Solanum lycopersicum seed oil freeze-dried powder is an ideal raw material for preparing a whitening drug and a cosmetic.

Abstract: A data transmission system and method thereof for edge computing are provided. A terminal mobile station international subscriber directory number (MSISDN) and a terminal IP of a target terminal are obtained with a domain name system (DNS) by a device providing communication services from the data transmission system. After data packets are sent to the data transmission system, if the target terminal is in an idle mode, a paging message is sent by a terminal wake-up module to enable the target terminal to return to a connected mode for communication. Before a connection is established between the data transmission system and the target terminal, downlink data packets can be temporarily stored, and the packets can be sent after the target terminal is in the connected mode. A computer readable medium for executing the data transmission method is also provided.

Abstract: A clock synchronization method and apparatus, an electronic device and a storage medium are provided. The clock synchronization method includes: sending a trigger signal to a second processing module and recording a current count value of the first timer upon sending the trigger signal as a first count value; and reading a second count value from the second processing module, the second count value is a current count value of a second timer of the second processing module upon the second processing module receiving the trigger signal, and a count value of the second timer is used as a timing reference of the second processing module and sequentially increasing; the first count value and the second count value are used for a clock compensation to synchronize a first clock domain where the first processing module is located with a second clock domain where the second processing module is located.

Abstract: A method of radiating a plurality of masses in a patient is provided, including receiving a three-dimensional model of the patient, the model including respective locations of a plurality of OARs, receiving a set of locations in the model corresponding to the masses, respective prescribed radiation dosages for the masses, and respective radiation limits for the OARs. The method includes computing a candidate set of beams having respective beam paths that travel through at least one of the masses. The method includes scoring the candidate set of beams based on respective dosages provided to the masses, respective dosages provided to the OARs, and beams in a set of selected beams for treatment, adding a best-scoring beam among the candidate set of beams to the set of selected beams, and radiating the masses using the set of selected beams.

Abstract: A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data one by one; and write the n intermediate data and a sign signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the sign signal; different values of the sign signal respectively represent different processing processes of the first data processing, and n is a positive integer.

Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.

Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.