Patents by Inventor Shang-Yun Hou
Shang-Yun Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11810793Abstract: One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 ?m thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.Type: GrantFiled: July 26, 2022Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
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Publication number: 20230350142Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.Type: ApplicationFiled: July 5, 2023Publication date: November 2, 2023Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Sung-Hui Huang, Kuan-Yu Huang, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
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Publication number: 20230307375Abstract: A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.Type: ApplicationFiled: January 9, 2023Publication date: September 28, 2023Inventors: Hao-Cheng Hou, Tsung-Ding Wang, Jung Wei Cheng, Yu-Min Liang, Chien-Hsun Lee, Shang-Yun Hou, Wei-Yu Chen, Collin Jordon Fleshman, Kuo-Lung Pan, Shu-Rong Chun, Sheng-Chi Lin
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Publication number: 20230307382Abstract: A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.Type: ApplicationFiled: June 1, 2023Publication date: September 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou
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Publication number: 20230307427Abstract: A method includes forming a build-up package substrate, which includes forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs, forming a first plurality of through-vias on the first plurality of RDLs, bonding an interconnect die to the second plurality of RDLs, encapsulating the interconnect die and the first plurality of through-vias in a first encapsulant, and forming a third plurality of RDLs over the first encapsulant. The third plurality of RDLs are electrically connected to the first plurality of through-vias. An organic package substrate is bonded to the build-up package substrate. The build-up package substrate and the organic package substrate in combination form a compound organic package substrate. A first package component and a second package component are bonded to the compound organic package substrate, and are electrically interconnected through the interconnect die.Type: ApplicationFiled: June 10, 2022Publication date: September 28, 2023Inventors: Sheng-Chi Lin, Hao-Cheng Hou, Tsung-Ding Wang, Chien-Hsun Lee, Shang-Yun Hou
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Publication number: 20230299033Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.Type: ApplicationFiled: May 26, 2023Publication date: September 21, 2023Inventors: Kuan-Yu Huang, Li-Chung Kuo, Sung-Hui Huang, Shang-Yun Hou, Tsung-Yu Chen, Chien-Yuan Huang
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Patent number: 11764123Abstract: A semiconductor package includes a substrate, a stacked structure, an encapsulation material, a lid structure, and a coupler. The stacked structure is disposed over and bonded to the substrate. The encapsulation material partially encapsulates the stacked structure. The lid structure is disposed on the substrate, wherein the lid structure surrounds the stacked structure and covers a top surface of the stacked structure. The coupler is bonded to the stacked structure, wherein a portion of the coupler penetrates through and extends out of the lid structure.Type: GrantFiled: July 4, 2022Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Hui Huang, Shang-Yun Hou, Tien-Yu Huang, Heh-Chang Huang, Kuan-Yu Huang, Shu-Chia Hsu, Yu-Shun Lin
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Patent number: 11747563Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.Type: GrantFiled: August 10, 2022Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsing-Kuo Hsia, Chen-Hua Yu, Kuo-Chiang Ting, Shang-Yun Hou
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Publication number: 20230260896Abstract: A device package including an interposer. The interposer comprising: a semiconductor substrate; first through vias extending through the semiconductor substrate; an interconnect structure comprising: a first metallization pattern in an inorganic insulating material; and a passivation film over the first metallization pattern; and a first redistribution structure over the passivation film. The first redistribution structure comprising a second metallization pattern in an organic insulating material. The device package further including an integrated circuit die over and attached to the interposer; and a first encapsulant around the integrated circuit die.Type: ApplicationFiled: June 10, 2022Publication date: August 17, 2023Inventors: Hsien-Pin Hu, Shang-Yun Hou, Shih-Wen Huang
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Patent number: 11728254Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.Type: GrantFiled: May 22, 2020Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
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Patent number: 11705407Abstract: A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.Type: GrantFiled: March 3, 2022Date of Patent: July 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou
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Patent number: 11699674Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.Type: GrantFiled: August 23, 2021Date of Patent: July 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuan-Yu Huang, Li-Chung Kuo, Sung-Hui Huang, Shang-Yun Hou, Tsung-Yu Chen, Chien-Yuan Huang
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Patent number: 11694939Abstract: A semiconductor package includes a substrate, a stacked structure, an encapsulation material, a lid structure, and a coupler. The stacked structure is disposed over and bonded to the substrate. The encapsulation material partially encapsulates the stacked structure. The lid structure is disposed on the substrate, wherein the lid structure surrounds the stacked structure and covers a top surface of the stacked structure. The coupler is bonded to the stacked structure, wherein a portion of the coupler penetrates through and extends out of the lid structure.Type: GrantFiled: May 22, 2020Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Hui Huang, Shang-Yun Hou, Tien-Yu Huang, Heh-Chang Huang, Kuan-Yu Huang, Shu-Chia Hsu, Yu-Shun Lin
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Patent number: 11682593Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.Type: GrantFiled: July 20, 2020Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng
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Publication number: 20230124804Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
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Patent number: 11630271Abstract: A package structure is provided. The package structure includes a waveguide, a passivation layer, and a reflector. The waveguide is over a substrate. The passivation layer is over the substrate and covers the waveguide. The reflector includes a metal layer and a semiconductor layer on the passivation layer. The metal layer and the first semiconductor layer are in contact with the passivation layer.Type: GrantFiled: July 26, 2022Date of Patent: April 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sung-Hui Huang, Jui-Hsieh Lai, Shang-Yun Hou
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Publication number: 20230085054Abstract: A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The first electronic component is between the second and the third electronic components. The first interconnection structures are between the first and the second electronic components. Each first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component, and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between the second and the third electronic components, and electrically connected to the second and the third electronic components. A height of each second interconnection structure is different from a height of each first interconnection structure.Type: ApplicationFiled: November 20, 2022Publication date: March 16, 2023Inventors: WEIMING CHRIS CHEN, TU-HAO YU, KUO-CHIANG TING, SHANG-YUN HOU, CHI-HSI WU
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Patent number: 11592618Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.Type: GrantFiled: April 9, 2021Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsing-Kuo Hsia, Chen-Hua Yu, Kuo-Chiang Ting, Shang-Yun Hou
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Patent number: 11569156Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, connective terminals and supports. The circuit substrate has a first side and a second side opposite to the first side. The semiconductor package is connected to the first side of the circuit substrate. The connective terminals are located on the second side of the circuit substrate and are electrically connected to the semiconductor package via the circuit substrate. The supports are located on the second side of the circuit substrate beside the connective terminals. A material of the supports has a melting temperature higher than a melting temperature of the connective terminals.Type: GrantFiled: February 23, 2020Date of Patent: January 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou
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Patent number: 11569172Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.Type: GrantFiled: May 29, 2020Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shang-Yun Hou, Hsien-Pin Hu