Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

Abstract: A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

Abstract: A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.

Abstract: A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a dummy bump over a second surface of the first substrate. The first surface is opposite the second surface, and the dummy bump is electrically insulated from the chip. The method includes cutting through the first substrate and the dummy bump to form a cut substrate and a cut dummy bump. The cut dummy bump is over a corner portion of the cut substrate, a first sidewall of the cut dummy bump is substantially coplanar with a second sidewall of the cut substrate, and a third sidewall of the cut dummy bump is substantially coplanar with a fourth sidewall of the cut substrate.

Abstract: A structure and a formation method of a package structure are provided. The method includes forming one or more solder elements over a substrate. The one or more solder elements surround a region of the substrate. The method also includes disposing a semiconductor die structure over the region of the substrate. The method further includes dispensing a polymer-containing liquid onto the region of the substrate. The one or more solder elements confine the polymer-containing liquid to being substantially inside the region. In addition, the method includes curing the polymer-containing liquid to form an underfill material.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.

Abstract: A package structure is provided. The package structure includes an optical component over a substrate, and a reflector disposed over the substrate. The reflector includes a first semiconductor layer over a second semiconductor layer, and a dielectric layer between the first semiconductor layer and the second semiconductor layer. The reflector also includes a metal layer between the second semiconductor layer and the substrate. In addition, the package structure includes a waveguide between the metal layer and the optical component.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a substrate, a first chip stack attached to the substrate, and a second chip stack attached to the substrate. The first chip stack and the second chip stack being attached to a same side of the substrate. The chip package further includes a molding compound layer surrounding the first chip stack and the second chip stack. The molding compound layer covers a topmost surface of the first chip stack. A topmost surface of the molding compound layer is substantially coplanar with a topmost surface of the second chip stack.

Abstract: A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.

Abstract: A package structure is provided. The package structure includes an optical component over a substrate, and a reflector disposed over the substrate. The reflector includes a first semiconductor layer over a second semiconductor layer, and a dielectric layer between the first semiconductor layer and the second semiconductor layer. The reflector also includes a metal layer between the second semiconductor layer and the substrate. In addition, the package structure includes a waveguide between the metal layer and the optical component.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad.

Abstract: A semiconductor device includes a dielectric interposer, a first interconnection layer, an electronic component, a plurality of electrical conductors and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first interconnection layer is over the first surface of the dielectric interposer. The electronic component is over and electrically connected to the first interconnection layer. The electrical conductors are over the second surface of the dielectric interposer. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first interconnection layer and the electrical conductors.

Abstract: A package system includes a first interposer including a first substrate having first and second primary surfaces on opposite sides of the first substrate. The package system includes a first interconnect structure over the first surface, the first interconnect structure having a first metallic line pitch LP1. The package system includes a plurality of first through silicon via (TSV) structures in the first substrate. The package system includes a molding compound material partially enveloping the first substrate. The package system includes a plurality of through vias in the molding compound material, wherein each through via of the plurality of through vias is offset from the first substrate. The package system includes a second interconnect structure on a second surface of the first substrate. The second interconnect structure has a second metallic line pitch LP2, and LP2>LP1. The package system includes a first integrated circuit over the first interposer.

Abstract: A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The second electronic component is between the first electronic component and the third electronic component. The first interconnection structures are between and electrically connected to the first electronic component and the second electronic component. Each of the first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between and electrically connected to the second electronic component and the third electronic component.

Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.